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| 型號： | DSP56303VF100R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 76/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 100MHZ 196-BGA |
| 標準包裝： | 750 |
| 系列： | DSP563xx |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 100MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 24kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 帶卷 (TR) |
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Power
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
1-3
1.1 Power
1.2 Ground
Table 1-2.
Power Inputs
Power Name
Description
VCCP
PLL Power—VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with
an extremely low impedance path to the VCC power rail.
VCCQ
Quiet Power—An isolated power for the core processing logic. This input must be isolated externally from all other chip
power inputs.
VCCA
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied externally
to all other chip power inputs,
except VCCQ.
VCCD
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally to all
other chip power inputs,
except VCCQ.
VCCC
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all other
chip power inputs,
except VCCQ.
VCCH
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all other chip power
inputs,
except VCCQ.
VCCS
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be tied
externally to all other chip power inputs,
except VCCQ.
Note: The user must provide adequate external decoupling capacitors for all power connections.
Table 1-3.
Grounds1
Ground Name
Description
GNDP
PLL Ground—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip
package.
GNDP1
PLL Ground 1—Ground-dedicated for PLL use. The connection should be provided with an extremely low-impedance
path to ground.
GNDQ
2
Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied externally to all other
chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling capacitors.
GNDA
2
Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This connection must be tied
externally to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external
decoupling capacitors.
GNDD
2
Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection must be tied externally
to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling
capacitors.
GNDC
2
Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be tied externally to all
other chip ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling
capacitors.
GNDH
2
Host Ground—An isolated ground for the HI08 I/O drivers. This connection must be tied externally to all other chip
ground connections, except GNDP and GNDP1. The user must provide adequate external decoupling capacitors.
GNDS
2
ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This connection must be
tied externally to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate external
decoupling capacitors.
GND3
Ground—Connected to an internal device ground plane.
Notes:
1.
The user must provide adequate external decoupling capacitors for all GND connections.
2.
These connections are only used on the TQFP package.
3.
These connections are common grounds used on the MAP-BGA package.
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