參數資料
型號: DS2407V
英文描述: Dual Addressable Switch Plus 1K.Bit Memory
中文描述: 雙尋址開關與1K.Bit記憶
文件頁數: 26/31頁
文件大?。?/td> 194K
代理商: DS2407V
DS2407
012099 26/31
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated
in Figure 15. All time slots are initiated by the master
driving the data line low. The falling edge of the data line
synchronizes the DS2407 to the master by triggering a
delay circuit in the DS2407. During write time slots, the
delay circuit determines when the DS2407 will sample
the data line. For a read data time slot, if a “0” is to be
transmitted, the delay circuit determines how long the
DS2407 will hold the data line low overriding the 1 gen-
erated by the master. If the data bit is an “1”, the device
will leave the read data time slot unchanged.
PROGRAM PULSE
To copy data from the 8–bit scratchpad to the EPROM
Data or Status Memory, a program pulse of 12 volts is
applied to the data line after the bus master has con-
firmed that the CRC for the current byte is correct. Dur-
ing programming, the bus master controls the transition
from a state where the data line is idling high via the
pull–up resistor to a state where the data line is actively
driven to a programming voltage of 12 volts providing a
minimum of 10 mA of current to the DS2407. This pro-
gramming voltage (Figure 16) should be applied for 480
μ
s, after which the bus master should return the data
line to an idle high state controlled by the pull–up resis-
tor. Note that due to the high voltage programming
requirements for any 1–Wire EPROM device, it is not
possible to multi–drop non–EPROM based 1–Wire
devices (e.g. DS1990A, DS1992) with the DS2407 dur-
ing programming. An internal diode within the non–
EPROM based 1–Wire devices will attempt to clamp the
data line at approximately 8 volts and could potentially
damage these DS199x devices.
CRC GENERATION
With the DS2407 there are two different types of CRCs
(Cyclic Redundancy Checks). One CRC is an 8–bit type
and is stored in the most significant byte of the 64–bit
ROM. The bus master can compute a CRC value from
the first 56 bits of the 64–bit ROM and compare it to the
value stored within the DS2407 to determine if the ROM
data has been received error–free by the bus master.
The equivalent polynomial function of this CRC is:
X
8
+ X
5
+ X
4
+ 1. This 8–bit CRC is received in the true
(non–inverted) form when reading the ROM of the
DS2407. It is computed at the factory and lasered into
the ROM.
The other CRC is a 16–bit type, generated according to
the standardized CRC16–polynomial function X
16
+ X
15
+ X
2
+ 1. This CRC is used for error detection when
reading Data Memory, Status Memory or when commu-
nicating with PIO channels. It is the same type of CRC
as is used with NVRAM based iButtons for error detec-
tion within the iButton Extended File Structure. In con-
trast to the 8–bit CRC, the 16–bit CRC is always
returned in the complemented (inverted) form. A CRC–
generator inside the DS2407 chip (Figure 17) will calcu-
late a new 16–bit CRC at every situation shown in the
command flow chart of Figure 6.
The DS2407 provides this CRC–value to the bus mas-
ter to validate the transfer of command, address, and
data to and from the bus master. When reading the data
memory of the DS2407 with the Read Memory com-
mand, the 16–bit CRC is only transmitted at the end of
the memory. This CRC is generated by clearing the
CRC generator, shifting in the command, low address,
high address and every data byte starting at the first
addressed memory location and continuing until the end
of the implemented data memory is reached.
When reading the Status Memory with the Read Status
command, the 16–bit CRC is transmitted at the end of
the 8 byte page of the Status Memory. The 16–bit CRC
will be generated by clearing the CRC generator, shift-
ing in the command byte, low address, high address and
the data bytes beginning at the first addressed memory
location and continuing until the last byte of the EPROM
Status Memory is reached.
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