參數(shù)資料
型號: DS2407V
英文描述: Dual Addressable Switch Plus 1K.Bit Memory
中文描述: 雙尋址開關(guān)與1K.Bit記憶
文件頁數(shù): 25/31頁
文件大?。?/td> 194K
代理商: DS2407V
DS2407
012099 25/31
READ/WRITE TIMING DIAGRAM
Figure 15 (cont’d)
Write–zero Time Slot
V
PULLUP
V
PULLUP MIN
IH MIN
V
IL MAX
t
SLOT
t
REC
t
LOW0
SAMPDS2407
60
μ
s
15
μ
s
60
μ
s < t
LOW0
< t
SLOT
< 120
μ
s
1
μ
s < t
REC
<
Read–data Time Slot
V
PULLUP
V
PULLUP MIN
IH MIN
V
IL MAX
0V
t
SLOT
t
REC
t
RDV
t
LOWR
60
μ
s < t
SLOT
< 120
μ
s
1
μ
s < t
LOWR
< 15
μ
s
0 < t
RELEASE
< 45
μ
s
1
μ
s < t
REC
<
t
RDV
= 15
μ
s
t
SU
< 1
μ
s
t
RELEASE
MASWINDOW
RESISTOR
MASTER
DS2407
t
SU
1–WIRE SIGNALING
The DS2407 requires strict protocols to insure data
integrity. The protocol consists of five types of signaling
on one line: Reset Sequence with Reset Pulse and
Presence Pulse, Write 0, Write 1, Read Data and Pro-
gram Pulse. All these signals except presence pulse are
initiated by the bus master. The initialization sequence
required to begin any communication with the DS2407
is shown in Figure 14. A reset pulse followed by a pres-
ence pulse indicates the DS2407 is ready to accept a
ROM command. The bus master transmits (TX) a reset
pulse (t
RSTL
, minimum 480
μ
s). The bus master then
releases the line and goes into receive mode (RX). The
1–Wire bus is pulled to a high state via the pull–up resis-
tor. After detecting the rising edge on the data pin, the
DS2407 waits (t
PDH
, 15–60
μ
s) and then transmits the
presence pulse (t
PDL
, 60–240
μ
s). If the device is pro-
grammed to power–up into the “Hidden Mode”, the
presence pulse will be observed only once during the
power–up phase. With every subsequent reset pulse no
presence pulse will be transmitted.
相關(guān)PDF資料
PDF描述
DS2407X Dual Addressable Switch Plus 1K.Bit Memory
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