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參數(shù)資料
| 型號： | DS21Q44T |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 15/105頁 |
| 文件大?。?/td> | 620K |
| 代理商： | DS21Q44T |
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DS21Q44
15 of 105
RECEIVE SIDE PINS
Signal Name:
Signal Description:
Signal Type:
Updated with full recovered E1 data stream on the rising edge of RCLK.
RLINK
Receive Link Data
Output
Signal Name:
Signal Description:
Signal Type:
A 4 KHz to 20 KHz clock for the RLINK output. Used for sampling Sa bits.
RLCLK
Receive Link Clock
Output
Signal Name:
Signal Description:
Signal Type:
2.048 MHz clock that is used to clock data through the receive side framer.
RCLK
Receive Clock Input
Input
Signal Name:
Signal Description:
Signal Type:
A 256 KHz clock which pulses high during the LSB of each channel. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with RSYSCLK when the receive side elastic store is
enabled. Useful for parallel to serial conversion of channel data. This function is available when FMS = 1
(DS21Q43 emulation).
RCHCLK
Receive Channel Clock
Output
Signal Name:
Signal Description:
Signal Type:
A user programmable output that can be forced high or low during any of the 32 E1 channels.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD
controller in applications where not all E1 channels are used such as Fractional E1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert applications, for
external per–channel loopback, and for per–channel conditioning. See Section 12 for details.
RCHBLK
Receive Channel Block
Output
Signal Name:
Signal Description:
Signal Type:
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
RSER
Receive Serial Data
Output
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC
multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an
input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.
RSYNC
Receive Sync
Input /Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21Q44TN | MICROSWITCH, SPDT, SIM ROLLER LEVER; Current, contact AC:5A; Force, operating:91.75gf; Travel, pre:16.0mm; Centres, fixing LxW:22.2mm; Temp, op. max:120(degree C); Temp, op. min:-40(degree C); Length / Height, external:9.25mm; Width, RoHS Compliant: Yes |
| DS2251T-128-16 | CONNECTOR ACCESSORY |
| DS2251T-32-16 | 128k Soft Microcontroller Module |
| DS2251T-64-16 | CONNECTOR ACCESSORY |
| DS2251 | 128k Soft Microcontroller Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q44T+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q44TN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48A3N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48B | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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