參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 152/160頁
文件大小: 559K
代理商: DS2196LN
DS2196
91 of 160
15.1
BERT REGISTER DESCRIPTION
BC0: BERT CONTROL REGISTER 0 (Address = 40 Hex)
(MSB)
(LSB)
TINV
RINV
PS2
PS1
PS0
LC
RESYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
BC0.7
Not Assigned. Should be set to 0 when written to.
TINV
BC0.6
Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
RINV
BC0.5
Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
PS2
BC0.4
Pattern Select Bit 2. Refer to Table 15-1 for details.
PS1
BC0.3
Pattern Select Bit 1. Refer to Table 15-1 for details.
PS0
BC0.2
Pattern Select Bit 0. Refer to Table 15-1 for details.
LC
BC0.1
Load Bit and Error Counters (LC). A low to high transition
latches the current bit and error counts into the host accessible
registers BBC0/BBC1/BBC2/BBC3 and BEC0/BEC1/BEC2
and clears the internal count. This bit should be toggled from
low to high whenever the host wishes to begin a new
acquisition period. Must be cleared and set again for a
subsequent loads.
RESYNC
BC0.0
Force Resynchronization (RESYNC). A low to high
transition will force the receive BERT synchronizer to
resynchronize to the incoming data stream. This bit should be
toggled from low to high whenever the host wishes to acquire
synchronization on a new pattern. Must be cleared and set
again for a subsequent resynchronization.
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