參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 108/160頁
文件大小: 559K
代理商: DS2196LN
DS2196
51 of 160
(MSB)
(LSB)
RJC
EAMS
MECU
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION
NAME AND DESCRIPTION
RJC
CCR6B.7
Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
EAMS
CCR6B.6
Error Accumulation Mode Select.
0 = CCR3B.2 determines accumulation time
1 = CCR6B.5 determines accumulation time
MECU
CCR6B.5
Manual Error Counter Update. When enabled by CCR6B.6,
the changing of this bit from a 0 to a 1 allows the next clock
cycle to load the error counter registers with the latest counts
and reset the counters. The user must wait a minimum of 972
ns (1.5 clock periods) before reading the error count registers to
allow for proper update.
RCM4
CCR6B.4
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 10 for details.
RCM3
CCR6B.3
Receive Channel Monitor Bit 3.
RCM2
CCR6B.2
Receive Channel Monitor Bit 2.
RCM1
CCR6B.1
Receive Channel Monitor Bit 1.
RCM0
CCR6B.0
Receive Channel Monitor Bit 0. LSB of the channel decode.
相關PDF資料
PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
DS21FF44N DATACOM, FRAMER, PBGA300
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
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