參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 135/160頁
文件大小: 559K
代理商: DS2196LN
DS2196
76 of 160
TIR1A/TIR2A/TIR3A: TRANSMIT IDLE REGISTERS FRAMER A
(Address = 3C to 3E Hex)
TIR1B/TIR2B/TIR3B: TRANSMIT IDLE REGISTERS FRAMER B
(Address = DC to DE Hex)
[Also used for Per–Channel Loopback]
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TIR1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TIR2
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TIR3
SYMBOLS
POSITIONS
NAME AND DESCRIPTION
CH1-24
TIR1.0-3.7
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
NOTE:
If CCR4.0=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies
that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel Loopback;
see Figure 1–1).
TIDRA: TRANSMIT IDLE DEFINITION REGISTER FRAMER A
(Address = 3F Hex)
TIDRB: TRANSMIT IDLE DEFINITION REGISTER FRAMER B
(Address = DF Hex)
(MSB)
(LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION
NAME AND DESCRIPTION
TIDR7
TIDR.7
MSB of the Idle Code (this bit is transmitted first)
TIDR0
TIDR.0
LSB of the Idle Code (this bit is transmitted last)
11.2
RECEIVE SIDE CODE GENERATION
The Receive Mark Registers (RMR1/2/3) are used to determine which of the 24 T1 channels should be
overwritten with either a 7Fh idle code or with a digital milliwatt pattern. The RCR2.7 bit will determine
which code is used. The digital milliwatt code is an eight-byte repeating pattern that represents a 1 kHz
sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RMRs, represents a particular channel. If a bit is
set to a 1, then the receive data in that channel will be replaced with one of the two codes. If a bit is set to
0, no replacement occurs.
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