
DS2196
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LIST OF FIGURES
Figure 1-1: T1 Dual Framer LIU..............................................................................................................9
Figure 15-1: BERT Mux Diagram ..........................................................................................................87
Figure 19-1: External Analog Connections..........................................................................................121
Figure 19-2: Jitter Tolerance.................................................................................................................122
Figure 19-3: Transmit Waveform Template........................................................................................122
Figure 19-4: Jitter Attenuation..............................................................................................................123
Figure 20-1: Boundary Scan Architecture...........................................................................................124
Figure 20-2: TAP Controller State Machine........................................................................................127
Figure 21-1: Receive Side D4 Timing....................................................................................................133
Figure 21-2: Receive Side ESF Timing.................................................................................................134
Figure 21-3: Receive Side Boundary Timing .......................................................................................135
Figure 21-4: Transmit Side D4 Timing.................................................................................................136
Figure 21-5: Transmit Side ESF Timing..............................................................................................137
Figure 21-6: Transmit Side Boundary Timing ....................................................................................138
Figure 21-7: Transmit Data Flow..........................................................................................................139
Figure 21-8: Receive Data Flow.............................................................................................................140
Figure 22-1: Intel Bus Read AC Timing (BTS=0 / MUX = 1) ............................................................146
Figure 22-2: Intel Bus Write Timing (BTS=0 / MUX=1)....................................................................147
Figure 22-3: Motorola Bus AC Timing (BTS = 1 / MUX = 1)............................................................148
Figure 22-4: Intel Bus Read AC Timing (BTS=0 / MUX=0) ..............................................................149
Figure 22-5: Intel Bus Write AC Timing (BTS=0 / MUX=0).............................................................150
Figure 22-6: Motorola Bus Read AC Timing (BTS=1 / MUX=0) ......................................................151
Figure 22-7: Motorola Bus Write AC Timing (BTS=1 / MUX=0).....................................................152
Figure 22-8: Receive Side AC Timing...................................................................................................153
Figure 22-9: Receive Line Interface AC Timing..................................................................................154
Figure 22-10: Transmit Side AC Timing..............................................................................................155
Figure 22-11: Transmit Line Interface Side AC Timing.....................................................................156