參數(shù)資料
型號： DS2196
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 14/157頁
文件大?。?/td> 734K
代理商： DS2196
DS2196
14 of 157
Signal Description:
Signal Type:
Updated on the rising edge of TCLKA or TCLKB with either bipolar data or a frame sync pulse out of the transmit
side formatter. This pin can be programmed to source the frame sync pulse via the Output Data Format (CCR1A.6
and CCR1B.6) control bits.
TNEGA/B / TFSYNCA/B
Transmit Negative Data & Frame Sync Pulse Output
Output
Receive Framer Pins
Signal Name:
Signal Description:
Signal Type:
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If RCHCLK is selected, a
192-kHz clock, which pulses high during the LSB of each channel, will be output. If RLCLK is selected, either a 4
kHz or 2 kHz (ZBTSI) clock for the RLINK data is output. This output signal is always synchronous with RCLKA
or RCLKB.
RCHCLKA/B / RLCLKA/B
Receive Channel Clock / Receive Link Clock
Output
Signal Name:
Signal Description:
Signal Type:
A dual function pin depending on the setting of the CCR4A.1 and CCR4B.1 control bits. If RCHBLK is selected, a
user programmable output that can be forced high or low during any of the 24 T1 channels. Useful for blocking
clocks to a serial UART or LAPD controller in applications where not all T1 channels are used such as Fractional
T1, 384 kbps service, 768 kbps, or ISDN–PRI. Also useful for locating individual channels in drop–and–insert
applications, for external per–channel loopback, and for per–channel conditioning. See Section 21 for details. If
RLINK is selected, then either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLKA before the start of a
frame are output. See Section 21 for details. This signal is always synchronous with RCLKA or RCLKB.
RCHBLKA/B / RLINKA/B
Receive Channel Block / Receive Link Data
Output
Signal Name:
Signal Description:
Signal Type:
Received NRZ serial data. Updated on rising edges of RCLKA or RCLKB.
RSERA/B
Receive Serial Data
Output
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLKA or RCLKB wide, is output at this pin which identifies frame boundaries. Via
RCR2A.5 and RCR2B.5, RFSYNC can also be set to output double–wide pulses on signaling frames. This signal
is always synchronous with RCLKA or RCLKB
.
RFSYNCA/B
Receive Frame Sync
Output
Signal Name:
Signal Description:
Signal Type:
An extracted pulse, one RCLKA or RCLKB wide, is output at this pin which identifies multiframe boundaries.
This signal is always synchronous with RCLKA or RCLKB.
RMSYNCA/B
Receive Multiframe Sync
Output
相關(guān)PDF資料
PDF描述
DS2196L Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS2196LN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43AT Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43ATN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2196L 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:T1 Dual Framer LIU
DS2196LN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Dual Framer LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2196LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Dual Framer LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS219T 功能描述:烙鐵 DESOLDERING HEAD RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included
DS21E352 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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