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參數(shù)資料
| 型號： | DS1982 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | UniqueWare iButton(UniqueWare iButton標準的EPROM) |
| 中文描述： | 1K位只添加iButton® |
| 文件頁數(shù)： | 16/21頁 |
| 文件大小： | 139K |
| 代理商： | DS1982 |
DS1982
062598 16/21
Skip ROM [CCH]
This command can save time in a single drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64–bit ROM code. If
more than one slave is present on the bus and a read
command is issued following the Skip ROM command,
data collision will occur on the bus as multiple slaves
transmit simultaneously (open drain pull–downs will
produce a wire–AND result).
Search ROM [F0H]
When a system is initially brought up, the bus master
might not know the number of devices on the 1–Wire
bus or their 64–bit ROM codes. The search ROM com-
mand allows the bus master to use a process of elimina-
tion to identify the 64–bit ROM codes of all slave devices
on the bus. The ROM search process is the repetition of
a simple 3–step routine: read a bit, read the complement
of the bit, then write the desired value of that bit. The bus
master performs this simple, 3–step routine on each bit
of the ROM. After one complete pass, the bus master
knows the contents of the ROM in one device. The
remaining number of devices and their ROM codes may
be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive
discussion of a ROM search, including an actual exam-
ple.
1–Wire Signaling
The DS1982 requires strict protocols to insure data
integrity. The protocol consists of five types of signaling
on one line: Reset Sequence with Reset Pulse and
Presence Pulse, Write 0, Write 1, Read Data and Pro-
gram Pulse. All these signals except presence pulse are
initiated by the bus master. The initialization sequence
required to begin any communication with the DS1982
is shown in Figure 10. A reset pulse followed by a pres-
ence pulse indicates the DS1982 is ready to accept a
ROM command. The bus master transmits (TX) a reset
pulse (t
RSTL
, minimum 480
μ
s). The bus master then
releases the line and goes into receive mode (RX). The
1–Wire bus is pulled to a high state via the pull–up resis-
tor. After detecting the rising edge on the 1–Wire line,
the DS1982 waits (t
PDH
, 15–60
μ
s) and then transmits
the presence pulse (t
PDL
, 60–240
μ
s).
Read/Write Time Slots
The definitions of write and read time slots are illustrated
in Figure 11. All time slots are initiated by the master
driving the data line low. The falling edge of the data line
synchronizes the DS1982 to the master by triggering a
delay circuit in the DS1982. During write time slots, the
delay circuit determines when the DS1982 will sample
the data line. For a read data time slot, if a “0” is to be
transmitted, the delay circuit determines how long the
DS1982 will hold the data line low overriding the 1 gen-
erated by the master. If the data bit is a “1”, the iButton
will leave the read data time slot unchanged.
PROGRAM PULSE
To copy data from the 8–bit scratchpad to the EPROM
Data or Status Memory, a program pulse of 12 volts is
applied to the data line after the bus master has con-
firmed that the CRC for the current byte is correct. Dur-
ing programming, the bus master controls the transition
from a state where the data line is idling high via the
pull–up resistor to a state where the data line is actively
driven to a programming voltage of 12 volts providing a
minimum of 10 mA of current to the DS1982. This pro-
gramming voltage (Figure 12) should be applied for 480
μ
s, after which the bus master returns the data line to an
idle high state controlled by the pull–up resistor. Note
that due to the high voltage programming requirements
for any 1–Wire EPROM device, it is not possible to mul-
ti–drop non–EPROM based 1–Wire devices with the
DS1982 during programming. An internal diode within
the non–EPROM based 1–Wire devices will attempt to
clamp the data line at approximately 8 volts and could
potentially damage these devices.
CRC GENERATION
The DS1982 has an 8–bit CRC stored in the most signif-
icant byte of the 64–bit ROM. The bus master can com-
pute a CRC value from the first 56 bits of the 64–bit ROM
and compare it to the value stored within the DS1982 to
determine if the ROM data has been received error–free
by the bus master. The equivalent polynomial function
of this CRC is: X
8
+ X
5
+ X
4
+ 1.
Under certain conditions, the DS1982 also generates
an 8–bit CRC value using the same polynomial function
shown above and provides this value to the bus master
to validate the transfer of command, address, and data
bytes from the bus master to the DS1982. The Memory
Function Flow Chart of Figure 6 indicates that the
DS1982 computes an 8–bit CRC for the command,
address, and data bytes received for the Write Memory
and the Write Status commands and then outputs this
value to the bus master to confirm proper transfer. Simi-
larly the DS1982 computes an 8–bit CRC for the com-
mand and address bytes received from the bus master
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| DS2045W | 3.3V Single-Piece 1Mb Nonvolatile SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS1982+F3 | 制造商:Maxim Integrated Products 功能描述:1KB ADD-ONLY IBTN 2PIN F3 MICROCAN - Rail/Tube |
| DS1982+F5 | 制造商:Maxim Integrated Products 功能描述:1KB ADD-ONLY IBTN 2PIN F5 MICROCAN - Rail/Tube 制造商:Maxim Integrated Products 功能描述:IC MEMORY I BUTTON 1982 |
| DS1982-F3 | 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1982-F3# | 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1982-F3+ | 功能描述:iButton 1Kb Add-Only iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
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