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參數(shù)資料
| 型號： | DS1982 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | UniqueWare iButton(UniqueWare iButton標準的EPROM) |
| 中文描述： | 1K位只添加iButton® |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 139K |
| 代理商： | DS1982 |
DS1982
062598 13/21
1–WIRE BUS SYSTEM
The 1–Wire bus is a system which has a single bus mas-
ter and one or more slaves. In all instances, the DS1982
is a slave device. The bus master is typically a micro-
controller. The discussion of this bus system is broken
down into three topics: hardware configuration, trans-
action sequence, and 1–Wire signaling (signal type and
timing). A 1–Wire protocol defines bus transactions in
terms of the bus state during specified time slots that are
initiated on the falling edge of sync pulses from the bus
master. For a more detailed protocol description, refer to
Chapter 4 of the Book of DS19xx iButton Standards.
Hardware Configuration
The 1–Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive it
at the appropriate time. To facilitate this, each device
attached to the 1–Wire bus must have an open drain
connection or 3–state outputs. The DS1982 is an open
drain part with an internal circuit equivalent to that
shown in Figure 7. The bus master can be the same
equivalent circuit. If a bidirectional pin is not available,
separate output and input pins can be tied together.
The bus master requires a pull–up resistor at the master
end of the bus, with the bus master circuit equivalent to
the one shown in Figures 8a and 8b. The value of the
pull–up resistor should be approximately 5 k
for short
line lengths.
A multidrop bus consists of a 1–Wire bus with multiple
slaves attached. The 1–Wire bus has a maximum data
rate of 16.3k bits per second. If the bus master is also
required to perform programming of the EPROM por-
tions of the DS1982, a programming supply capable of
delivering up to 10 milliamps at 12 volts for 480
μ
s is
required. The idle state for the 1–Wire bus is high. If, for
any reason, a transaction needs to be suspended, the
bus MUST be left in the idle state if the transaction is to
resume. If this does not occur and the bus is left low for
more than 120
μ
s, one or more of the devices on the bus
may be reset.
TRANSACTION SEQUENCE
The sequence for accessing the DS1982 via the 1–Wire
port is as follows:
Initialization
ROM Function Command
Memory Function Command
Read/Write Memory/Status
INITIALIZATION
All transactions on the 1–Wire bus begin with an initial-
ization sequence. The initialization sequence consists
of a reset pulse transmitted by the bus master followed
by a presence pulse(s) transmitted by the slave(s).
The presence pulse lets the bus master know that the
DS1982 is on the bus and is ready to operate. For more
details, see the “1–Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can
issue one of the four ROM function commands. All ROM
function commands are eight bits long. A list of these
commands follows (refer to flowchart in Figure 9):
Read ROM [33H]
This command allows the bus master to read the
DS1982’s 8–bit family code, unique 48–bit serial num-
ber, and 8–bit CRC. This command can be used only if
there is a single DS1982 on the bus. If more than one
slave is present on the bus, a data collision will occur
when all slaves try to transmit at the same time (open
drain will produce a wired–AND result).
Match ROM [55H]
The match ROM command, followed by a 64–bit ROM
sequence, allows the bus master to address a specific
DS1982 on a multidrop bus. Only the DS1982 that
exactly matches the 64–bit ROM sequence will respond
to the subsequent memory function command. All
slaves that do not match the 64–bit ROM sequence will
wait for a reset pulse. This command can be used with a
single or multiple devices on the bus.
相關PDF資料 |
PDF描述 |
|---|---|
| DS1985 | UniqueWare iButton(唯一貨品按鈕) |
| DS1986U | UniqueWare iButton(唯一貨品按鈕) |
| DS1986 | 64K bit Add-Only iButton(64K位只加按鈕) |
| DS2045W | 3.3V Single-Piece 1Mb Nonvolatile SRAM |
| DS2045W-100 | 3.3V Single-Piece 1Mb Nonvolatile SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS1982+F3 | 制造商:Maxim Integrated Products 功能描述:1KB ADD-ONLY IBTN 2PIN F3 MICROCAN - Rail/Tube |
| DS1982+F5 | 制造商:Maxim Integrated Products 功能描述:1KB ADD-ONLY IBTN 2PIN F5 MICROCAN - Rail/Tube 制造商:Maxim Integrated Products 功能描述:IC MEMORY I BUTTON 1982 |
| DS1982-F3 | 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1982-F3# | 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
| DS1982-F3+ | 功能描述:iButton 1Kb Add-Only iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated |
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