參數(shù)資料
型號: DS1982
廠商: Maxim Integrated Products, Inc.
英文描述: UniqueWare iButton(UniqueWare iButton標(biāo)準(zhǔn)的EPROM)
中文描述: 1K位只添加iButton®
文件頁數(shù): 12/21頁
文件大小: 139K
代理商: DS1982
DS1982
062598 12/21
agrees with the 8–bit CRC calculated by the DS1982. If
an incorrect CRC is ignored and a program pulse is
applied by the bus master, incorrect programming could
occur within the DS1982. Also note that the DS1982 will
always increment its internal address counter after the
receipt of the eight read time slots used to confirm the
programming of the selected EPROM byte. The deci-
sion to continue is again made entirely by the bus mas-
ter, therefore if the EPROM data byte does not match
the supplied data byte but the master continues with the
Write Memory command, incorrect programming could
occur within the DS1982. The Write Memory command
sequence can be exited at any point by issuing a Reset
Pulse.
WRITE STATUS [55H]
The Write Status command is used to program the
EPROM Status data field. The bus master will follow the
command byte with a two byte starting address
(TA1=(T7:T0), TA2=(T15:T8)) and a byte of status data
(D7:D0). An 8–bit CRC of the command byte, address
bytes, and data byte is computed by the DS1982 and
read back by the bus master to confirm that the correct
command word, starting address, and data byte were
received.
If the CRC read by the bus master is incorrect, a Reset
Pulse must be issued and the entire sequence must be
repeated. If the CRC received by the bus master is cor-
rect, a programming pulse (12 volts on the 1–Wire bus
for 480
μ
s) is issued by the bus master. Prior to program-
ming, the first seven bytes of the EPROM Status data
field will appear as logical 1s. For each bit in the data
byte provided by the bus master that is set to a logical 0,
the corresponding bit in the selected byte of the EPROM
Status data field will be programmed to a logical 0 after
the programming pulse has been applied at that byte
location. The eighth byte of the EPROM Status Byte
data field is factory–programmed to contain 00h.
After the 480
μ
s programming pulse is applied and the
data line returns to a 5 volt level, the bus master issues
eight read time slots to verify that the appropriate bits
have been programmed. The DS1982 responds with
the data from the selected EPROM Status address sent
least significant bit first. This byte contains the logical
AND of all bytes written to this EPROM Status Byte
address. If the EPROM Status Byte contains 1s in bit
positions where the byte issued by the master contained
0s, a Reset Pulse should be issued and the current byte
address should be programmed again. If the DS1982
EPROM Status Byte contains 0s in the same bit posi-
tions as the data byte, the programming was successful
and the DS1982 will automatically increment its address
counter to select the next byte in the EPROM Status
data field. The least significant byte of the new two–byte
address will also be loaded into the 8–bit CRC generator
as a starting value. The bus master will issue the next
byte of data using eight write time slots.
As the DS1982 receives this byte of data into the
scratchpad, it also shifts the data into the CRC genera-
tor that has been preloaded with the LSB of the current
address and the result is an 8–bit CRC of the new data
byte and the LSB of the new address. After supplying
the data byte, the bus master will read this 8–bit CRC
from the DS1982 with eight read time slots to confirm
that the address incremented properly and the data byte
was received correctly. If the CRC is incorrect, a Reset
Pulse must be issued and the Write Status command
sequence must be restarted. If the CRC is correct, the
bus master will issue a programming pulse and the
selected byte in memory will be programmed.
Note that the initial pass through the Write Status flow
chart will generate an 8–bit CRC value that is the result
of shifting the command byte into the CRC generator,
followed by the two address bytes, and finally the data
byte. Subsequent passes through the Write Status flow
chart due to the DS1982 automatically incrementing its
address counter will generate an 8–bit CRC that is the
result of loading (not shifting) the LSB of the new
(incremented) address into the CRC generator and then
shifting in the new data byte.
For both of these cases, the decision to continue (to
apply a program pulse to the DS1982) is made entirely
by the bus master, since the DS1982 will not be able to
determine if the 8–bit CRC calculated by the bus master
agrees with the 8–bit CRC calculated by the DS1982. If
an incorrect CRC is ignored and a program pulse is
applied by the bus master, incorrect programming could
occur within the DS1982. Also note that the DS1982 will
always increment its internal address counter after the
receipt of the eight read time slots used to confirm the
programming of the selected EPROM byte. The deci-
sion to continue is again made entirely by the bus mas-
ter, therefore if the EPROM data byte does not match
the supplied data byte but the master continues with the
Write Status command, incorrect programming could
occur within the DS1982. The Write Status command
sequence can be ended at any point by issuing a Reset
Pulse.
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