參數(shù)資料
型號: DS1982
廠商: Maxim Integrated Products, Inc.
英文描述: UniqueWare iButton(UniqueWare iButton標(biāo)準(zhǔn)的EPROM)
中文描述: 1K位只添加iButton®
文件頁數(shù): 11/21頁
文件大?。?/td> 139K
代理商: DS1982
DS1982
062598 11/21
mand only generates an 8–bit CRC at the end of
memory space that often might be ignored, since in
many applications the user would store a 16–bit CRC
with the data itself in each page of the 1024–bit EPROM
data field at the time the page was programmed.
The Read Data/Generate 8–bit CRC command pro-
vides an alternate read capability for applications that
are “bit–oriented” rather than “page–oriented” where
the 1024–bit EPROM information may change over time
within a page boundary making it impossible to program
the page once and include an accompanying CRC that
will always be valid. Therefore, the Read Data/Generate
8–Bit CRC command concludes each page with the
DS1982 generating and supplying an 8–bit CRC that is
based on and therefore is always consistent with the
current data stored in each page of the 1024–bit
EPROM data field. After the 8–bit CRC of the last page
is read, the bus master will receive logical 1s from the
DS1982 until a Reset Pulse is issued. The Read Data/
Generate 8–Bit CRC command sequence can be exited
at any point by issuing a Reset Pulse.
WRITE MEMORY [0FH]
The Write Memory command is used to program the
1024–bit EPROM data field. The bus master will follow
the command byte with a two byte starting address
(TA1=(T7:T0), TA2=(T15:T8)) and a byte of data
(D7:D0). An 8–bit CRC of the command byte, address
bytes, and data byte is computed by the DS1982 and
read back by the bus master to confirm that the correct
command word, starting address, and data byte were
received.
The highest starting address within the DS1982 is
007FH. If the bus master sends a starting address
higher than this, the nine most significant address bits
are set to zero by the internal circuitry of the chip. This
will result in a mismatch between the CRC calculated by
the DS1982 and the CRC calculated by the bus master,
indicating an error condition.
If the CRC read by the bus master is incorrect, a Reset
Pulse must be issued and the entire sequence must be
repeated. If the CRC received by the bus master is cor-
rect, a programming pulse (12 volts on the 1–Wire bus
for 480
μ
s) is issued by the bus master. Prior to program-
ming, the entire unprogrammed 1024–bit EPROM data
field will appear as logical 1s. For each bit in the data
byte provided by the bus master that is set to a logical 0,
the corresponding bit in the selected byte of the
1024–bit EPROM will be programmed to a logical 0 after
the programming pulse has been applied at that byte
location.
After the 480
μ
s programming pulse is applied and the
data line returns to a 5 volt level, the bus master issues
eight read time slots to verify that the appropriate bits
have been programmed. The DS1982 responds with
the data from the selected EPROM address sent least
significant bit first. This byte contains the logical AND of
all bytes written to this EPROM data address. If the
EPROM data byte contains 1s in bit positions where the
byte issued by the master contains 0s, a Reset Pulse
should be issued and the current byte address should
be programmed again. If the DS1982 EPROM data byte
contains 0s in the same bit positions as the data byte,
the programming was successful and the DS1982 will
automatically increment its address counter to select
the next byte in the 1024–bit EPROM data field. The
least significant byte of the new two byte address will
also be loaded into the 8–bit CRC generator as a start-
ing value. The bus master will issue the next byte of data
using eight write time slots.
As the DS1982 receives this byte of data into the
scratchpad, it also shifts the data into the CRC genera-
tor that has been preloaded with the LSB of the current
address and the result is an 8–bit CRC of the new data
byte and the LSB of the new address. After supplying
the data byte, the bus master will read this 8–bit CRC
from the DS1982 with eight read time slots to confirm
that the address incremented properly and the data byte
was received correctly. If the CRC is incorrect, a Reset
Pulse must be issued and the Write Memory command
sequence must be restarted. If the CRC is correct, the
bus master will issue a programming pulse and the
selected byte in memory will be programmed.
Note that the initial pass through the Write Memory flow
chart will generate an 8–bit CRC value that is the result
of shifting the command byte into the CRC generator,
followed by the two address bytes, and finally the data
byte. Subsequent passes through the Write Memory
flow chart due to the DS1982 automatically increment-
ing its address counter will generate an 8–bit CRC that
is the result of loading (not shifting) the LSB of the new
(incremented) address into the CRC generator and then
shifting in the new data byte.
For both of these cases, the decision to continue (to
apply a program pulse to the DS1982) is made entirely
by the bus master, since the DS1982 will not be able to
determine if the 8–bit CRC calculated by the bus master
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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DS1982-F3 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated
DS1982-F3# 功能描述:iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated
DS1982-F3+ 功能描述:iButton 1Kb Add-Only iButton RoHS:否 存儲類型:SRAM 存儲容量:512 B 組織: 工作電源電壓:3 V to 5.25 V 接口類型:1-Wire 最大工作溫度:+ 85 C 尺寸:17.35 mm x 5.89 mm 封裝 / 箱體:F5 MicroCan 制造商:Maxim Integrated