參數(shù)資料
型號(hào): DS16EV5110ASQX/NOPB
廠商: National Semiconductor
文件頁(yè)數(shù): 23/24頁(yè)
文件大?。?/td> 0K
描述: IC EQUALIZER VIDEO 3D+C 48-LLP
產(chǎn)品培訓(xùn)模塊: Signal Conditioning Applications
標(biāo)準(zhǔn)包裝: 2,500
類型: 視頻均衡器
應(yīng)用: HD 顯示器,DVI/HDMI
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-LLP(7x7)
包裝: 帶卷 (TR)
其它名稱: DS16EV5110ASQX
SNLS301C – JULY 2008 – REVISED APRIL 2013
SYSTEM MANAGEMENT BUS (SMBUS) AND CONFIGURATION REGISTERS
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. The use of the
Chip Select signal is required. Holding the CS pin High enables the SMBus port allowing access to the
configuration registers. Holding the CS pin Low disables the device's SMBus allowing communication from the
host to other slave devices on the bus. In the STANDBY state, the System Management Bus remains active.
When communication to other devices on the SMBus is active, the CS signal for the DS16EV5110As must be
driven Low.
The address byte for all DS16EV5110As is AC'h. Based on the SMBus 2.0 specification, the DS16EV5110A has
a 7-bit slave address of 1010110'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 1100 'b or
AC'h.
The SDC and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not
5V tolerant.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SDC is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SDC is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SDC is High indicates a message STOP condition.
IDLE: If SDC and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus Transactions
The device supports WRITE and READ transactions. See Table 1 for register address, type (Read/Write, Read
Only), default value and function information.
Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
6. The Host drive the 8-bit data byte.
7. The Device drives an ACK bit (“0”).
8. The Host drives a STOP condition.
9. The Host de-selects the device by driving its SMBus CS signal Low.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host (Master) selects the device by driving its SMBus Chip Select (CS) signal High.
2. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
3. The Device (Slave) drives the ACK bit (“0”).
4. The Host drives the 8-bit Register Address.
5. The Device drives an ACK bit (“0”).
6. The Host drives a START condition.
7. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
8. The Device drives an ACK bit “0”.
8
Copyright 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS16EV5110A
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