參數(shù)資料
型號(hào)： DS16EV5110ASQX/NOPB
廠商： National Semiconductor
文件頁(yè)數(shù)： 21/24頁(yè)
文件大?。?/td> 0K
描述： IC EQUALIZER VIDEO 3D+C 48-LLP
產(chǎn)品培訓(xùn)模塊： Signal Conditioning Applications
標(biāo)準(zhǔn)包裝： 2,500
類型： 視頻均衡器
應(yīng)用： HD 顯示器，DVI/HDMI
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-LLP（7x7）
包裝： 帶卷 (TR)
其它名稱： DS16EV5110ASQX
SNLS301C – JULY 2008 – REVISED APRIL 2013
Electrical Characteristics — System Management Bus Interface
(1) (2)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
System Bus Interface — DC Specifications
VIL
Data, Clock Input Low Voltage
0.8
V
VIH
Data, Clock Input High Voltage
2.8
VDD
V
IPULLUP
Current through pull-up resistor or
VOL = 0.4V
10
mA
current source
VDD
Nominal Bus Voltage
3.0
3.6
V
ILEAK-Bus
Input Leakage per bus segment
(3)
-200
+200
A
ILEAK-Pin
Input Leakage per device pin
-15
A
CI
Capacitance for SDA and SDC
(3) (4)
10
pF
RTERM
Termination Resistance
VDD3.3,
(3) (4) (5)
1000
System Bus Interface Timing Specification
FSMB
Bus Operating Frequency
(6)
10
100
kHz
TBUF
Bus Free Time Between Stop and
4.7
s
Start Condition
TSU:CS
Minimum time between SMB_CS
(7)
30
ns
being active and start condition
TH:CS
Minimum time between stop
(7)
100
ns
condition and releasing SMB_CS
THD:STA
Hold Time After (Repeated) Start
At IPULLUP, Max
Condition. First CLK generated
4.0
s
after this period.
TSU:STA
Repeated Start Condition Setup
4.7
s
Time
TSU:STO
Stop Condition Setup Time
4.0
s
THD:DAT
Data Hold Time
300
ns
TSU:DAT
Data Setup Time
250
ns
TTIMEOUT
Detect Clock Low Timeout
(6)
25
35
ms
TLOW
Clock Low Period
4.7
s
THIGH
Clock High Period
(6)
4.0
50
s
TLOW:SEXT
Cumulative Clock Low Extend Time
(6)
2
ms
(Slave Device)
tF
Clock/Data Fall Time
(6)
300
ns
tR
Clock/Data Rise Time
(6)
1000
ns
tPOR
Time in which a device must be
(6)
500
ms
operational after power-on reset
(1)
Typical values represent most likely parametric norms at VDD = 3.3V, TA = 25°C, and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
(2)
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes.
(3)
Recommended value. Parameter not tested in production.
(4)
Recommended maximum capacitance load per bus segment is 400pF.
(5)
Maximum termination voltage should be identical to the device supply voltage.
(6)
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
(7)
Specification is ensured by characterization and is not tested in production.
6
Copyright 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS16EV5110A
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