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參數(shù)資料
| 型號： | DS1280 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3-Wire to Bytewide Converter Chip(3線至字節(jié)寬度（8位）轉(zhuǎn)換芯片) |
| 中文描述： | 3線，以Bytewide轉(zhuǎn)換器芯片（3線至字節(jié)寬度（8位）轉(zhuǎn)換芯片） |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 132K |
| 代理商： | DS1280 |
DS1280
021998 6/11
use and uniquely identify each. A read can occur suc-
cessfully without knowing the select bits but a write can-
not occur without matching the current select field.
A third command masking specific select bits provides a
means for determining the identity of a specific DS1280
when more than one is used. A read in the read/write
field and a ‘‘11000” in the command field will execute a
mask read that ignores all select bits to determine the
presence of one or more DS1280s. With the detection
of at least one device, a search can begin by masking all
but a single pair of DS1280 select bits. A read in the
read/write field and a ‘‘11001” in the command field will
unmask the first two LSBs of byte 4 of the select bits
(see Figure 3). With these two select bits unmasked,
only an exact match of four possible combinations of
these two select bits will allow access through the 3-wire
port to RAM. The combinations are 00, 01, 10, and 11.
Therefore, repeating the unmasking of the first two bits
of the select field up to four times will give the binary val-
ue of these select bits.
Having determined the first two select bits, the next two
select bits can be unmasked, and the process of match-
ing one of four combinations can proceed as before.
Repetition of unmasking select bit pairs will yield an ex-
act match of 65,536 possible DS1280s in no more than
32 attempts.
ARBITRATION
As mentioned earlier, one byte of RAM has been re-
served for arbitration between the 3-wire port and the
bytewide parallel bus. The location of this byte within
the memory map will be at address 00000 or at address
7FFFF as determined by the protocol input from the
3-wire serial port. The arbitration byte has special re-
strictions and disciplines so that the 3-wire serial bus
and the bytewide parallel bus are never in contention for
RAM access. This byte is shown in Figure 4.
As defined, the 3-wire serial port can read the whole
byte but can only write bits S2-S0. The bytewide paral-
lel port can read the whole byte but can only write bits
B1-B0. An internal counter controls bits C2-C0 that can-
not be written by either port. Arbitration is accomplished
when the status bits are read and written by the respec-
tive ports. If the 3-wire serial port wants to access RAM,
the arbitration byte should be polled by the serial port
until bit B1 equals zero. If B1 equals zero, the 3-wire se-
rial port should then write a one into bit S2. After the
write of bit S2, the 3-wire serial port should then read the
arbitration byte to confirm that B1=0 and S2=1. This op-
eration must be executed with the protocol for the com-
pressed read/write/read sequence which minimizes
overhead.
The 3-wire serial port should always abort any attempt
to access RAM if B1 equals one. When the 3-wire serial
port completes any transfer of data to or from RAM, bit
S2 should be written back to zero so that the bytewide
parallel port will know that the 3-wire serial port is not us-
ing the RAM. The bytewide serial bus can gain access
to RAM by polling the arbitration byte until S2 bit equals
zero. When S2 equals zero, the bytewide parallel port
then writes a one into bit B1. A read cycle verifying that
S2 equals zero and B1 equals one confirms that the by-
tewide parallel port has access to RAM. The bytewide
parallel port can then read or write RAM as required.
When the entire transaction is complete, the bytewide
parallel port should write the B1 bit to zero, signaling the
3-wire serial port that the RAM is not in use.
The bits B0, S1, and S0 can be defined by the user to
pass additional arbitration information, making possible
more elaborate handshaking schemes between the two
ports. Some typical uses for these bits could be an indi-
cation that a port desires access to RAM or the amount
of RAM written. Another method of arbitration between
the 3-wire serial port and the bytewide parallel bus is the
use of the count bits C0-C2. The 3-wire port reads or
writes from RAM only once every eight clock cycles.
This action occurs when the internal byte counter transi-
tions from a ‘‘111” state to a ‘‘000” state. The access oc-
curs regardless of the arbitration byte status bits. C0-C2
are updated as the internal serial bit counter is increm-
ented. The bytewide port can execute reads or writes
depending on the status of C0-C2. These bits indicate
the number of bits the 3-wire serial port has loaded and,
therefore, indicate when a read or write will occur from
the 3-wire port.
Since the 3-wire port always reads or writes at the ends
of a byte (C0-C2 = 1) the bytewide parallel bus should
never access RAM if the count bits read all ones. The
bytewide parallel port can determine the minimum time
left before the 3-wire serial port will access the memory
from the count bits and the minimum clock cycle applied
to the 3-wire clock input. Essentially the 3-wire serial
port is given priority on access to RAM and the bytewide
parallel port determines when it can access the RAM to
avoid colliding with the 3-wire serial port.
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