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參數(shù)資料
| 型號： | DS1280 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3-Wire to Bytewide Converter Chip(3線至字節(jié)寬度（8位）轉(zhuǎn)換芯片) |
| 中文描述： | 3線，以Bytewide轉(zhuǎn)換器芯片（3線至字節(jié)寬度（8位）轉(zhuǎn)換芯片） |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 132K |
| 代理商： | DS1280 |
DS1280
021998 2/11
PIN DESCRIPTION
RST
– The 3-wire serial port selection signal input.
When RST is low, all communications to the serial port
are inhibited. When high, data is clocked into or out of
the serial port.
CLK –
The clock input signal is used to input or extract
data from the 3-wire serial port. A clock cycle is defined
as a falling edge followed by a rising edge. Data is driv-
en out onto the 3-wire bus after a falling edge during
read cycles and latched into the port on the rising edge
during write cycles.
DQ –
The DQ signal is the bidirectional data signal for
the 3-wire serial port. Byte 0 bit 0 is the first bit input/out-
put.
DQE –
The DQE output signal is active (high level)
whenever the 3-wire serial port is driving the DQ line.
Therefore, this pin will be high whenever data is being
read. Otherwise it will be low and the DQ line will be an
input. This signal can be used as a means of tri-stating
the DQ driver on the other end.
CER –
Chip enable output to RAM. This signal is as-
serted active (low) during RAM read or write cycles.
This signal is either derived from the system bus chip
enable (CEB) or from a 56-bit protocol provided by the
3-wire serial port and associated timing circuits.
WER –
Write enable output to RAM. This signal is as-
serted active (low) during RAM write cycles. This signal
is either derived from the system bus write enable
(WEB) or from a 56-bit protocol provided by the 3-wire
serial port and associated timing circuits.
OER –
Output enable to RAM. This signal is asserted
active (low) during RAM read cycles. This signal is ei-
ther derived from the system bus read enable (OEB) or
from a 56-bit protocol provided by the 3-wire serial port
and associated timing circuits.
A0R-A18R –
Addresses supplied to RAM. These sig-
nals allow access to up to 512K bytes of RAM controlled
by the DS1280. The addresses are either derived from
the system address bus (A0B-A18B) or from the proto-
col and internal binary counter provided by the 3-wire
serial port and associated timing circuits.
D0R–D7R –
Data bus supplied to RAM. These eight
signals comprise the bidirectional data bus between ex-
ternal bytewide RAM and the DS1280. This data bus is
either derived from the system data bus (D0B-D7B) or
from the protocol and data stream provided by the
3-wire serial port and associated timing circuits.
CEB –
System bus chip enable to the DS1280. This sig-
nal is used to generate the RAM chip enable for transfer
of data to and from the parallel system bus to RAM
(68-pin package only).
OEB –
System bus output enable (read) for transfer of
data from RAM to the parallel system bus (68-pin pack-
age only).
WEB –
System bus write enable to the DS1280. This
signal is used to generate the RAM write enable for
transfer of data from the parallel system bus to the RAM
(68-pin package only).
A0B-A18B –
System bus addresses to the DS1280.
These signals are used to specify the address location
for data transfer to and from RAM (68-pin package
only).
D0B-D7B –
System data bus to and from the DS1280.
This bidirectional bus is used to carry data to and from
the parallel system bus and RAM (68-pin package only).
Vcc –
+5volt power from the DS1280 (2 pins).
GND –
Ground for the DS1280 (2 pins).
OPERATION
Figure 1 illustrates the main elements of the DS1280.
As shown, the DS1280 has two major sections: a 3-wire
to bytewide converter and a serial/parallel multiplexer.
The source of the serial/parallel multiplexer is either a
3–wire serial port or a bytewide system bus. Arbitration
of the serial/parallel multiplexer is controlled by signals
from the 3-wire to bytewide converter. The 3-wire serial
port, therefore, has priority in accessing the RAM and
the methods used to avoid collisions are primarily di-
rected by the 3-wire to bytewide converter.
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