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參數(shù)資料
| 型號： | DS1280 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3-Wire to Bytewide Converter Chip(3線至字節(jié)寬度（8位）轉換芯片) |
| 中文描述： | 3線，以Bytewide轉換器芯片（3線至字節(jié)寬度（8位）轉換芯片） |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 132K |
| 代理商： | DS1280 |
DS1280
021998 3/11
DS1280 BLOCK DIAGRAM
Figure 1
DQE
RST
CLK
DQ
SERIAL
PORT
BUFFERS
SYSTEM
PORT
CONTROL
BUFFERS
SYSTEM
PARALLEL
PORT ADDRESS
BUFFERS
3-WIRE TO
BYTEWIDE
CONVERTER
SERIAL/PARALLEL
ADDRESS MUX
WITH ARBITRATION
BYTE DETECT
I/O BUFFERS WITH
ARBITRATION BYTE
AND DIRECTION
CONTROL LOGIC
SERIAL/SYSTEM
CONTROL MUX
A01-A18R
RAM ADDRESS BUS
D0R-D7R
RAM DATA BUS
D0B-D7B
SYSTEM
DATA BUS
A0B-A18B
SYSTEM
ADDRESS BUS
DS1280Q-68
DS1280Q-80
ONLY
CEB
OEB
WEB
CER
OER
WER
SYSTEM BYTEWIDE PARALLEL BUS
If the RST signal for the 3-wire serial port is low (inac-
tive), the bytewide parallel port can access associated
RAM directly. The bytewide parallel bus addresses
(A0B-A18B) and control signals (CEB, OEB and WEB)
are buffered by the DS1280 and become outputs
A0R-A18R, CER, OER, and WER respectively, which
are connected directly to RAM. The data input/output
signals (D0B-D7B) are internally buffered and sent to
RAM on the data input/output signals D0R-D7R. The
buffering is designed to handle bidirectional data trans-
fer. Data will be written from the bytewide parallel bus to
RAM when CEB and WEB inputs are both active (low).
The OEB signal is a ‘‘don’t care” signal during a write
cycle. Data is read from RAM via the byte wide parallel
port when CEB and OEB signals are both low and WEB
is high.
3-WIRE SERIAL BUS
If the RST signal for the 3-wire serial port is active (high),
the 3-wire to bytewide converter controls the RAM
through the control/address/data multiplexers. The
3-wire to bytewide converter uses a 56-bit protocol writ-
ten serially using RST, DQ, and CLK to determine the
action required and also the starting address location in
the RAM to be used. Data is entered into the 3-wire
while RST is high on the low-to-high transition of the
CLK signal provided the data is stable on the DQ line
with the proper setup and hold times. The last eight bits
of the 56-bit protocol are a cyclic redundancy check byte
(CRC) that ensures that all bits of the protocol have
been received correctly. If the 56 bits of protocol have
not been received correctly, further action will be
aborted. The CRC check byte can catch up to three
single bit errors within the 56-bit protocol and can also
be used on incoming and outgoing serial data streams
to check the integrity of data being read or written. More
discussion on CRC use and CRC generation will follow
later in this text.
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