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參數資料
| 型號： | DS1280 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3-Wire to Bytewide Converter Chip(3線至字節(jié)寬度（8位）轉換芯片) |
| 中文描述： | 3線，以Bytewide轉換器芯片（3線至字節(jié)寬度（8位）轉換芯片） |
| 文件頁數： | 4/11頁 |
| 文件大?。?/td> | 132K |
| 代理商： | DS1280 |
DS1280
021998 4/11
PROTOCOL: 3-WIRE SERIAL BUS
The 3-wire serial bus protocol can cause eight different
actions to occur as shown in Table 1.
The organization of the 56-bit protocol is shown in Fig-
ure 2. As defined, the first byte of the protocol deter-
mines whether the action which is to occur involves a
read or write. A read function is defined by the binary
pattern 11101000. This pattern, therefore, applies to
commands 1, 3, 5, and 6 of Table 1. A write function is
defined by the binary pattern 00010111. This pattern,
therefore, applies to commands 2, 4, 7, and 8 of Table 1.
Any other pattern which is entered into the read/write
field will cause further action to terminate. Additional dif-
ferentiation as to which read or write command is deter-
mined by the last five bits of the third byte of the protocol
called the command field. The control field bits are de-
fined in Table 2 .
A burst read uses a 19-bit address field which consists
of the second, third, and bits 0, 1, and 2 of the fourth byte
of the protocol to determine the starting address of infor-
mation to be read from RAM. The byte of data resident
in that location is loaded into an 8-bit shift register within
the DS1280. The byte of data is then transferred from
the shift register to the 3-wire bus by driving the DQ line
on the falling edge of the next eight clocks with the LSB
first. A burst write uses the same 19-bit address field to
determine the starting address of information to be writ-
ten into RAM. Data is shifted from the DQ line of the
3-wire bus into an 8-bit shift register within the DS1280
on the next eight rising clock edges. After a byte is
loaded, the data is written into the RAM location immedi-
ately after the rising edge of the eighth clock. Burst
reads and writes will continue on a byte-by-byte basis,
automatically incrementing the selected address by one
location for each successive byte.
PROTOCOL COMMANDS
Table 1
1. Burst read
2. Burst write
3. Read protocol select bits
4. Write protocol select bits
5. Burst read masking portions of the protocol
select bits
6. Read CRC register
7. Set the address arbitration byte location
8. Poll arbitration byte for status and control
Termination of a current operation will occur at any time
when RST is taken low. If a byte of data has been loaded
into the shift register, a write cycle is allowed to finish, so
corrupted data is not written into the RAM. If a full byte of
data has not been loaded into the shift register when
RST goes low, no writing occurs. Reads can be termi-
nated at any point since there is no potential for corrup-
tion of data. The read CRC command provides a meth-
od for checking the integrity of data sent over the 3-wire
bus. The CRC byte resides in the last byte (byte 6) of the
protocol. The 8-bit CRC byte not only operates on the
protocol bits as they are written in, but also on all data
that is written or read from RAM.
After a burst read or write has finished and RST has
gone low, the final value of the CRC is stored in the
DS1280. If a read CRC register command is issued, the
stored CRC value is driven onto the DQ line by the first
eight clock cycles after the protocol is received. The
CRC value generated by the DS1280 should match ex-
actly with the value generated in the host system which
is transmitting or receiving data on the other end of the
3-wire bus. If it does not, data has been corrupted and a
retransmission should occur. It should be noted that the
CRC for the previous transaction can only be obtained if
a read CRC command is issued immediately after RST
goes low to reset the DS1280, then high to accept a
read CRC command. If any other sequence is followed,
an intermediate CRC will be generated and stored
whenever RST goes low again, destroying the CRC val-
ue of interest. Generation of the CRC byte by the exter-
nal unit on the 3-wire bus will be covered later in this data
sheet.
COMMAND FIELD
Table 2
00110
10001
00011
10110
Burst read
Burst write
Read CRC register
Set arbitration byte address to 00000 or
7FFFF
Poll arbitration byte for access to RAM
Read protocol select bits
Write protocol select bits
Burst read masking portions of the select
bits
01001
00101
01110
11XXX
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