參數(shù)資料
型號(hào)： DMC73C168
英文描述： 8Bit Single Chip Microcontroller
中文描述： 8位單芯片微控制器
文件頁數(shù)： 53/90頁
文件大?。?/td> 742K
代理商： DMC73C168
53
8Bit Single Chip Microcontroller
DMC73C167
Table 5-32. P51 0133h MDATA I2C Master Data
Bit
7
6
5
4
3
2
1
0
R
Master Receive Data
W
Master Receive Data
Bit 7-0
MDATA. 8-Bit Parallel Read/Write Shift Register.
The receiving data will be read every time INT5_IF=1. Afterwards, the INT5_1F flag
should be cleared. The transmitting data will be written every time INT5_1F=1.
Afterwards, the INT5_1F flag should be cleared.
Table 5-33. P52 0134h HDC I2C Master High Duration
Bit
7
6
5
4
3
2
1
0
R
SCL High Duration Value
W
SCL High Duration Value
Table 5-34. P53 0135h LDC I2C Master Low Duration
Bit
R
W
7
6
5
4
3
2
1
0
SCL Low Duration Value
SCL Low
Duration Value
HDC and LDC. SCL High and Low Duration Counters.
These are 8-bit registers for SCL frequency control By changing the contents of
these registers, the serial clock frequency (SCL) can be changed. High or low
duration can be calculated by the following equations.
High Duration =
4 x (FFh - Value of HDC) + 8
Fosc (OSC frequency of CPU)
Low Duration =
(LODUTY = 0)
4 x (FFh - Value of LDC) + 8
Fosc (OSC frequency of CPU)
Low Duration =
(LODUTY = 1)
3 x 4 (FFh - Value of LDC) + 8
Fosc (OSC frequency of CPU)
US
US
US
￡￡á￡￡×￡￡
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