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參數(shù)資料
| 型號： | DMC73C168 |
| 英文描述： | 8Bit Single Chip Microcontroller |
| 中文描述： | 8位單芯片微控制器 |
| 文件頁數(shù)： | 50/90頁 |
| 文件大小： | 742K |
| 代理商： | DMC73C168 |
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50
8Bit Single Chip Microcontroller
DMC73C167
5.7.1 Master Mode
5.7.1.1 Master Control Register
Table 5-28. P48 013h MCTL0 I2C Master Control 0
Bit
RW
7
6
-
5
4
3
2
1
0
ACT
RSRT
LODUTY
MDIR
NACK
BCM1
BCM0
Bit 7
ACT. Activation of Start Condition (R/W)
On hardware reset, this bit will be 0. But just after this bit is set to 1, actual
transfer will start. Therefore, before writing 1 to this bit, MSTS, MDATA, HDC,
and LDC should be initialized first. As soon as the start condition is generated,
the ACT bit will be cleared automatically.
RSRT. Restart (R/W)
A data transfer is always terminated by a stop condition generated by the
master. However, if a master still wants to communicate on the bus or
change the data transfer direction, it can generate another start condition
and address the new slave without first generating a stop condition.
To do this, the bit can be set after keeping the following settings for more
than 4usec: ACT=0, BCM1=0, and BCM0=0. This bit will be reset
automatically just after the restart action is triggered.
LODUTY. Low-Duty Output (R/W)
0 = SCL (Serial clock) duty is dependent on the contents of the HDC and
LDC values.
1 = Enlarges the low duration time by three times the LDC value.
For example, if HDC:LDC=1:1, the SCL duty will be 1:3 if the LODUTY
bit is set.
MDIR. Master Data Direction (R/W)
0 = Transmits data to the slave device. The contents of MDATA will be
loaded onto the SDA line.
1 = Receiveds data from the slave device. The data from the SDA line will
be stored in the MDATA register. Regardless of the MDIR bit, the address
data is always transmitted to the SDA line by internal hardware.
NACK. No Generation of Acknowledgement (R/W)
A master receiver must signal the last data transfer cycle or the end of the
data transfer to the slave transmitter by not generating an acknowledgement
on the last byte clocked from the slave. Then the slave transmitter will release
the data line to allow the master to generate the stop condition.
0 = Generates an acknowledgement after one byte has been received.
1 = Does not generate and acknlowledgement after one byte has been received.
Bit 5
Bit 4
Bit 3
Bit 2
￡￡á￡￡×￡￡
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