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參數(shù)資料
| 型號： | DMC73C168 |
| 英文描述： | 8Bit Single Chip Microcontroller |
| 中文描述： | 8位單芯片微控制器 |
| 文件頁數(shù)： | 51/90頁 |
| 文件大小： | 742K |
| 代理商： | DMC73C168 |
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51
8Bit Single Chip Microcontroller
DMC73C167
Bit 1, 0
BCM 1,0 . Bus Mode 1 and Mode 0 (R/W)
When ACT = 1, these bit will be decoded as follows.
BCM1
BCM0
0
0
1 byte data transfer with every ACT = 1
1
0
Address output with start condition to salve.
0
1
Stop condition will be generated (no data transfer).
1
1
Prohibited for any case.
Table 5-29. P49 0131th MCTL1 I2C Master Control 1
Bit
R
W
7
6
X
0
5
X
0
4
X
0
3
X
0
2
1
0
X
0
ENABLE
SCLP
0
SCLSDA
0
Bit 7
ENABLE. Enables I2C Master Hardware (R/W)
0 = Stops I2C master hardware. This is same as H/W reset for I2C master module.
1 = Starts I2C master hardware.
SCLP (READ). SCL Port Input Data of I2C Bus.
0 = Logic low (0) level of SCL port.
1 = Logic high (1) level of SCL port.
SCLSDA (READ).
NAND gate buffered data of SCL, SDA port.
0 = Both SCL and SDA ports at high levels.
1 = At least one of SCL or SDA is at low level.
(WRITE). These bits should always be zero.
Bit 2
Bit 1
Bit 6-0
Note :
In the multi-master mode, the ENABLE bit should be set to 1 before the
start condition comes up from another master device.
Table 5-30. P57 0139h DFCTL I2C Digital Filter Control
Bit
7
6
5
4
3
2
1
0
R
DFON
0
Not Used
Bit 7
DFON. Digital Filter Control ON (R/W)
Narrow pulses on the SDA and SCL lines are rejected when the DFON bit is set to 1.
This bit is commonly used for master and slave operations.
0 = Digital Filtering Off.
1 = Digital Filtering On.
Note :
Do not set the DFON bit to 1 if the higher period of the SCL is less than 8us
(Spec: min 4us + Filter; max 4us). Please set to "0" for normal usage.
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