參數(shù)資料
型號: DM9102DE
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)NIC控制器
文件頁數(shù): 21/70頁
文件大?。?/td> 2245K
代理商: DM9102DE
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
21
6.2 Control and Status Registers (CR)
The DM9102D implements 16 control and status registers,
which can be accessed by the host. These CRs are double
long word aligned. All CRs are set to their default values by
Register
hardware or software reset unless otherwise specified. All
Control and Status Registers with their definitions and offset
from IO or memory Base Address are shown below:
Description
Offset from CSR
Base Address
00H
08H
10H
18H
20H
28H
30H
38H
40H
48H
50H
58H
60H
68H
70H
78H
Default value
after reset
DE000000H
FFFFFFFFH
FFFFFFFFH
00000000H
00000000H
FC000000H
02040000H
FFFE0000H
00000000H
000083F0H
FFFFFFFFH
FFFE0000H
FFFFFFXXH
XXXXXX00H
Unpredictable
00000000H
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
CR9
CR10
CR11
CR12
CR13
CR14
CR15
System Control Register
Transmit Descriptor Poll Demand
Receive Descriptor Poll Demand
Receive Descriptor Base Address Register
Transmit Descriptor Base Address Register
Network Status Report Register
Network Operation Mode Register
Interrupt Mask Register
Statistical Counter Register
External Management Access Register
Reserved
Reserved
PHY Status Register
Sample Frame Access Register
Sample Frame Data Register
Watchdog And Jabber Timer Register
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only
RW = Read/Write
RW/C = Read/Write and Clear
WO = Write only
RO/C = Read only and cleared after read.
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
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