參數(shù)資料
型號(hào): DM9102DE
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)NIC控制器
文件頁(yè)數(shù): 18/70頁(yè)
文件大?。?/td> 2245K
代理商: DM9102DE
18
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
6.1.10 Interrupt & Latency Configuration (xxxxxx3cH - PCIINT)
Bit
31:24
23:16
31
16
15
0
8
7
23
24
MAX_LAT
MIN_GNT
INT_PIN
INT_LINE
Maximum Latency Timer
Minimum Grant
Interrupt Pin
Interrupt Line
Default
28H
14H
Type
RO
RO
Description
Maximum Latency Timer that can be sustained.
Minimum Grant
Minimum Length of a Burst Period.
Interrupt Pin read as 01H to indicate INTA#
Interrupt Line that Is routed to the Interrupt Controller
The value depends on system software.
15:8
7:0
01H
XXH
RO
RW
6.1.11 Device Specific Configuration Register (xxxxxx40H- PCIUSR)
3130 29
16 15
8
0
Reserved
27 26
28
7
25 24 23
Device Specific
Link Event enable/disable
Sample Frame Event enable/disable
Magic Packet Event enable/disable
Link Event Status
Sample Frame Event Status
Magic Packet Event Status
Device Specific
Reserved
Bit
31
30
29
28
27
26
25
Default
0
0
0
0
0
0
0
Type
RW
RW
RW
RW
RW
RO
RO
Description
Device Specific Bit (sleep mode)
Device Specific Bit (snooze mode)
When set, enables Link Status Change Wake up Event
When set, enables Sample Frame Wake up Event
When set, enables Magic Packet Wake up Event
When set, indicates the Link Change and the Link Status Change Event occurred
When set, indicates the Sample Frame is received and the Sample Frame match
Event occurred
When set, indicates the Magic Packet is received and the Magic packet Event
occurred
Reserved Bits Read As 0
Device Specific
Reserved Bits Read As 0
24
0
RO
23:16
15:8
7:0
00H
00H
00H
RO
RW
RO
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