- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376802 > DM9000E (Electronic Theatre Controls, Inc.) ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY PDF資料下載
參數(shù)資料
| 型號： | DM9000E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| 中文描述： | ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 19/54頁 |
| 文件大?。?/td> | 575K |
| 代理商： | DM9000E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9000-DS-F02
June 26, 2002
19
6.22 Vendor ID Register (28H~29H)
Bit
Name
7:0
VIDH
7:0
VIDL
Default
0AH,RO
46H.RO
Description
Vendor ID High Byte (29H)
Vendor ID Low Byte (28H)
6.23 Product ID Register (2AH~2BH)
Bit
Name
7:0
PIDH
7:0
PIDL
Default
90H,RO
00H.RO
Description
Product ID High Byte (2BH)
Product ID Low Byte (2AH)
6.24 Chip Revision Register (2CH)
Bit
Name
7:0
CHIPR
Default
00H,RO
Description
CHIP Revision
6.25 Special Mode Control Register ( 2FH )
Bit
Name
7
SM_EN
6~3
RESERVED
2
FLC
1
FB1
0
FB0
Default
0,RW
0,RO
0,RW
0,RW
0,RW
Description
Special Mode Enable
Reserved
Force Late Collision
Force Longest Back-off time
Force Shortest Back-off time
6.26 Memory Data Read Command without Address Increment Register (F0H)
Bit
Name
Default
7:0
MRCMDX
X,RO
Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged
Description
6.27 Memory Data Read Command with Address Increment Register (F2H)
Bit
Name
Default
7:0
MRCMD
X,RO
Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
Description
6.28 Memory Data Read_address Register (F4H~F5H)
Bit
Name
Default
7:0
MDRAH
00H,R/W
7:0
MDRAL
00H,R/W
Description
Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1
Memory Data Read_ address Low Byte
6.29 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
7:0
MWCMDX
X,WO
Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9006CJ | Gate Expander |
| DM9006CN | Gate Expander |
| DM9009CJ | Dual 4-input NAND Gate |
| DM9009CN | Dual 4-input NAND Gate |
| DM9002CN | Quad 2-input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9000E-H | 功能描述:以太網(wǎng)開發(fā)工具 ETHERNET CONTROLLER HEADER BRD 50x40mm RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DM9000EP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 100LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 100LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 100LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Digital IC Case Style:LQFP; No. of Pins:100; Interface Type:MII; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9000電路圖-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:型號DM9000電路圖1 |
| DM9000電路圖-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DM9000電路圖-2 |
| DM9002CJ/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad 2-input NAND Gate |
發(fā)布緊急采購，3分鐘左右您將得到回復。