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參數(shù)資料
| 型號(hào)： | DM9000E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| 中文描述： | ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 16/54頁 |
| 文件大小： | 575K |
| 代理商： | DM9000E |
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
16
Final
Version: DM9000-DS-F02
June 26, 2002
6.10 Flow Control Threshold Register ( 09H )
Bit
Name
7:4
HWOT
Default
3H, RW
Description
RX FIFO High Water Overflow Threshold
Send a pause packet with pause_ time=FFFFH when the RX RAM free space is
less than this value., If this value is zero, its means no free RX SRAM space.
Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes)
RX FIFO Low Water Overflow Threshold
Send a pause packet with pause_time=0000 when RX SRAM free space is larger
than this value. This pause packet is enabled after the high water pause packet is
transmitted. Default SRAM free space is 8K-byte. Please do not exceed SRAM size
(1 unit=1K bytes)
3:0
LWOT
8H, RW
6.11 RX/TX Flow Control Register ( 0AH )
Bit
Name
7
TXP0
Default
0,RW
Description
TX Pause Packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = 0000h
TX Pause packet
Auto clears after pause packet transmission completion. Set to TX pause packet
with time = FFFFH
Force TX Pause Packet Enable
Enables the pause packet for high/low water threshold control
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when any packet
comes and RX SRAM is over BPHW
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW
RX Pause Packet Status, latch and read clearly
RX Pause Packet Current Status
Flow Control Enable
Set to enable the flow control mode (i.e. to disable TX function)
6
TXPF
0,RW
5
TXPEN
0,RW
4
BKPA
0,RW
3
BKPM
0,RW
2
1
0
RXPS
RXPCS
FLCE
0,R/C
0,RO
0,RW
6.12 EEPROM & PHY Control Register ( 0BH )
Bit
Name
7:6
RESERVED
5
REEP
4
WEP
3
EPOS
Default
0,RO
0,RW
0,RW
0,RW
Description
Reserved
Reload EEPROM. Driver needs to clear it up after the operation completes
Write EEPROM Enable
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
2
ERPRR
0,RW
1
ERPRW
0,RW
0
ERRE
0,RO
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PDF描述 |
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| DM9006CJ | Gate Expander |
| DM9006CN | Gate Expander |
| DM9009CJ | Dual 4-input NAND Gate |
| DM9009CN | Dual 4-input NAND Gate |
| DM9002CN | Quad 2-input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9000E-H | 功能描述:以太網(wǎng)開發(fā)工具 ETHERNET CONTROLLER HEADER BRD 50x40mm RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DM9000EP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 100LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 100LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 100LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Digital IC Case Style:LQFP; No. of Pins:100; Interface Type:MII; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9000電路圖-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:型號(hào)DM9000電路圖1 |
| DM9000電路圖-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DM9000電路圖-2 |
| DM9002CJ/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad 2-input NAND Gate |
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