參數(shù)資料
型號： DM9000AEP
廠商： Electronic Theatre Controls, Inc.
英文描述： Ethernet Controller with General Processor Interface
中文描述： 以太網(wǎng)控制器與通用處理器接口
文件頁數(shù)： 26/56頁
文件大小： 1744K
代理商： DM9000AEP
DM9000A
Ethernet Controller with General Processor Interface
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
26
8. PHY Register Description
Name
15
14
Reset
Loop
back
OL
0
0
T4
Cap.
Cap.
0
1
PHYID1
0
0
PHYID2
1
0
04 Auto-Neg.
Advertise
Page
Ack
05
Link Part.
Ability
Next
Page
06 Auto-Neg.
Expansio
n
16 Specifie
d
Config.
17 Specifie
d
Conf/Stat
18
10T
Conf/Stat
Enable
ADD
00
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Speed
select
1
TX HDX
Cap.
1
0
1
Remote
Fault
LP
RF
Auto-N
Enable
1
10 FDX
Cap.
1
0
1
Reserved
Power
Down
0
10 HDX
Cap.
1
0
1
Isolate
Restart
Auto-N
0
Full
Duplex
1
Coll.
Test
0
Reserved
CONTR
0
000_0000
Auto-N
Cap.
1
0
TX FDX
Reserved
Pream.
Supr.
1
0
Auto-N
Compl.
0
0
Remote
Fault
0
0
Link
Status
0
0
Version No.
0000
Jabber
Detect
0
0
Extd
Cap.
1
1
01
STATUS
0000
02
03
0
0
FC
Adv
LP
FC
0
1
1
Model No.
01010
TX HDX
Adv
LP
TX HDX
Next
FLP Rcv
T4
Adv
LP
T4
TX FDX
Adv
LP
TX FDX
10 FDX
Adv
LP
10 FDX
10 HDX
Adv
LP
10 HDX
Advertised Protocol Selector Field
LP
LP
Ack
Reserved
Link Partner Protocol Selector Field
Reserved
Pardet
Fault
LP Next
Pg Able
Next Pg
Able
New Pg
Rcv
LP AutoN
Cap.
BP
4B5B
BP
SCR
BP
ALIGN
BP_ADP
OK
Reserve
dr
TX
Reserve
d
Reserve
d
Force
100LNK
Reserve
d
Reserve
d
RPDCTR
-EN
Reset
St. Mch
Pream.
Supr.
Sleep
mode
Remote
LoopOut
100
FDX
100
HDX
10
FDX
10 HDX Reserve
d
Reverse
d
Reverse
d
PHY ADDR [4:0]
Auto-N. Monitor Bit [3:0]
Rsvd
LP
HBE
Enable
SQUE
Enable
JAB
Enable
Reserve
d
Reserved
Polarity
Reverse
19
PWDOR
Reserved
PD10DRV
PD100l
PDchip
PDcrm
PDaeq
PDdrv
PDecli
PDeclo
PD10
20
Specified
config
TSTSE1 TSTSE2 FORCE_
TXSD
FORCE_
FEF
Reserved
MDIX_C
NTL
AutoNeg
_llpbk
Mdix_fix
Value
Mdix_do
wn
MonSel1 MonSel0 Reserve
d
PD_valu
e
Key to Default
In the register description that follows, the default
column takes the form:
<Reset Value>, <Access Type> / <Attribute(s)>
Where
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s)>:
SC = Self clearing
P = Value permanently set
LL = Latching low
LH = Latching high
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