參數資料
型號: DM9000AEP
廠商: Electronic Theatre Controls, Inc.
英文描述: Ethernet Controller with General Processor Interface
中文描述: 以太網控制器與通用處理器接口
文件頁數: 21/56頁
文件大?。?/td> 1744K
代理商: DM9000AEP
DM9000A
Ethernet Controller with General Processor Interface
One Packet Mode
When set, only one packet transmit command can be issued before transmit
completed.
When cleared, at most two packet transmit command can be issued before
transmit completed.
Inter-Frame Gap Setting
0XXX: 96-bit
1000: 64-bit
1001: 72-bit
1010:80-bit
1011:88-bit
1100:96-bit
1101:104-bit
1110: 112-bit
1111:120-bit
Preliminary datasheet
Version: DM9000A-DS-P03
Apr. 21, 2005
21
4
ONEPM
PH0,RW
3~0
IFGS
PH0,RW
6.26 Operation Test Control Register ( 2EH )
Bit
Name
Default
Description
7~6
SCC
PH0,RW
System Clock Control
Set the internal system clock.
00: 50Mhz
01: 20MHz
10: 100MHz
11: Reserved
Reserved
Internal SRAM Output-Enable Always ON
Internal SRAM Chip-Select Always ON
Internal PHY operation mode for testing
5
4
3
RESERVED
SOE
SCS
PHYOP
PH0,RW
PH0,RW
PH0,RW
PH0,RW
2~0
6.27 Special Mode Control Register ( 2FH )
Bit
Name
7
SM_EN
6~3
RESERVED
2
FLC
1
FB1
0
FB0
Default
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
Description
Special Mode Enable
Reserved
Force Late Collision
Force Longest Back-off time
Force Shortest Back-off time
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