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| 型號(hào)： | DK-DEV-4SGX230N |
| 廠商： | Altera |
| 文件頁數(shù)： | 61/82頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEVELOPMENT STRATIX IV |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 特色產(chǎn)品： | Stratix? IV GX FPGA Development Kit |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Stratix® IV GX |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | EP4SGX230K |
| 所含物品： | 開發(fā)板、通用電源、纜線和軟件 |
| 產(chǎn)品目錄頁面： | 607 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | EP4SGX230KF40C3N-ND - IC STRATIX IV FPGA 230K 1517FBGA EP4SGX230KF40C3-ND - IC STRATIX IV FPGA 230K 1517FBGA EP4SGX230HF35C3N-ND - IC STRATIX IV GX 230K 1152-FBGA EP4SGX230HF35C3-ND - IC STRATIX IV GX 230K 1152-FBGA EP4SGX230FF35C3NES-ND - IC STRATIX IV GX 230K 1152-FBGA EP4SGX230FF35C3ES-ND - IC STRATIX IV GX 230K 1152-FBGA EP4SGX230DF29C3NES-ND - IC STRATIX IV GX 230K 780-FBGA EP4SGX230DF29C3ES-ND - IC STRATIX IV GX 230K 780-FBGA |
| 其它名稱： | 544-2594 |
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Stratix IV Device Handbook
March 2014
Altera Corporation
Volume 4: Device Datasheet and Addendum
TCCS
True Differential I/O Standards
—
100
—
100
—
100
ps
Emulated Differential I/o
Standards
—
250
—
250
—
250
ps
Receiver
True Differential I/O
Standards -
fHSDRDPA (data rate)
SERDES factor J = 3 to 10 (11)
150
—
1600
150
—
1250
150
—
1250
Mbps
fHSDR (data rate)
SERDES factor J = 3 to 10
—
—
—
Mbps
SERDES factor J = 2,
Uses DDR Registers
—
—
—
Mbps
SERDES factor J = 1,
Uses an SDR Register
—
—
—
Mbps
DPA Mode
DPA run length
—
10000
—
10000
—
10000
UI
Soft CDR mode
Soft-CDR PPM
tolerance
—
300
—
300
—
300
±
PPM
Non DPA Mode
Sampling Window
—
300
—
300
—
300
ps
Notes to Table 1–42:
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) For 820, 530, 360, and 290 density devices, the frequency is 762 MHz.
(5) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local)
that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(6) The maximum ideal frequency is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the
signal integrity simulation is clean.
(7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(8) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew
margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported.
(9) This is achieved by using the LVDS and DPA clock network.
(10) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(11) The fMAX specification is based on the fast clock used for serial data. The interface fMAX also depends on the parallel clock domain, which is design
dependent and requires timing analysis.
(12) This only applies to DPA and soft-CDR modes.
(13) This only applies to LVDS source synchronous mode.
Table 1–42. High-Speed I/O Specifications (1), (2) (Part 3 of 3)
Symbol
Conditions
–2/–2× Speed Grade
–3 Speed Grade
–4 Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DK-DEV-4SGX230N/C2 | 功能描述:EP4SGX230KF40C2N Stratix? IV GX FPGA Evaluation Board 制造商:altera 系列:Stratix? IV GX 零件狀態(tài):過期 類型:FPGA 配套使用產(chǎn)品/相關(guān)產(chǎn)品:EP4SGX230KF40C2N 內(nèi)容:板，線纜，電源 標(biāo)準(zhǔn)包裝:1 |
| DK-DEV-4SGX530N | 功能描述:可編程邏輯 IC 開發(fā)工具 FPGA Development Kit For EP4SGX530 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| DK-DEV-5AGTD7N | 功能描述:可編程邏輯 IC 開發(fā)工具 FPGA Development Kit For 5AGTD7K3F40I3N RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| DK-DEV-5AGXB3N/ES | 功能描述:可編程邏輯 IC 開發(fā)工具 FPGA Development Kit For 5AGXFB3H6F ES RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓: |
| DK-DEV-5ASTD5N | 功能描述:KIT DEV ARRIA V FPGA 制造商:altera 系列:Arria V ST 零件狀態(tài):在售 類型:FPGA 配套使用產(chǎn)品/相關(guān)產(chǎn)品:Arria? V ST 內(nèi)容:板 標(biāo)準(zhǔn)包裝:1 |
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