參數(shù)資料
型號(hào)： DK-DEV-4SGX230N
廠商： Altera
文件頁(yè)數(shù)： 10/82頁(yè)
文件大小： 0K
描述： KIT DEVELOPMENT STRATIX IV
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品： Stratix? IV GX FPGA Development Kit
標(biāo)準(zhǔn)包裝： 1
系列： Stratix® IV GX
類型： FPGA
適用于相關(guān)產(chǎn)品： EP4SGX230K
所含物品： 開發(fā)板、通用電源、纜線和軟件
產(chǎn)品目錄頁(yè)面： 607 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： EP4SGX230KF40C3N-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230KF40C3-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230HF35C3N-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230HF35C3-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3NES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3ES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230DF29C3NES-ND - IC STRATIX IV GX 230K 780-FBGA
EP4SGX230DF29C3ES-ND - IC STRATIX IV GX 230K 780-FBGA
其它名稱： 544-2594
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–10
Electrical Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 1–13 lists OCT variation with temperature and voltage after power-up
calibration. Use Table 1–13 to determine the OCT variation after power-up calibration
and Equation 1–1 to determine the OCT variation without re-calibration.
Table 1–13 lists the OCT variation after the power-up calibration.
Pin Capacitance
Table 1–14 lists the Stratix IV device family pin capacitance.
Equation 1–1. OCT Variation Without Re-Calibration (1), (2), (3), (4), (5), (6)
(1) The ROCT value calculated from Equation 1–1 shows the range of OCT resistance with the variation of temperature
and VCCIO.
(2) RSCAL is the OCT resistance value at power-up.
(3)
T is the variation of temperature with respect to the temperature at power-up.
(4)
V is the variation of voltage with respect to the V
CCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 1–13. OCT Variation after Power-Up Calibration (1)
Symbol
Description
VCCIO (V)
Typical
Unit
dR/dV
OCT variation with voltage without
re-calibration
3.0
0.0297
%/mV
2.5
0.0344
1.8
0.0499
1.5
0.0744
1.2
0.1241
dR/dT
OCT variation with temperature
without re-calibration
3.0
0.189
%/°C
2.5
0.208
1.8
0.266
1.5
0.273
1.2
0.317
Note to Table 1–13:
(1) Valid for VCCIO range of ±5% and temperature range of 0° to 85°C.
ROCT
RSCAL 1
dR
dT
-------
T
dR
dV
-------
V
+
=
Table 1–14. Pin Capacitance for Stratix IV Devices (Part 1 of 2)
Symbol
Description
Value
Unit
CIOTB
Input capacitance on the top and bottom I/O pins
4
pF
CIOLR
Input capacitance on the left and right I/O pins
4
pF
CCLKTB
Input capacitance on the top and bottom non-dedicated clock input pins
4
pF
CCLKLR
Input capacitance on the left and right non-dedicated clock input pins
4
pF
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