參數(shù)資料
型號(hào): DK-DEV-4SGX230N
廠商: Altera
文件頁數(shù): 24/82頁
文件大?。?/td> 0K
描述: KIT DEVELOPMENT STRATIX IV
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
特色產(chǎn)品: Stratix? IV GX FPGA Development Kit
標(biāo)準(zhǔn)包裝: 1
系列: Stratix® IV GX
類型: FPGA
適用于相關(guān)產(chǎn)品: EP4SGX230K
所含物品: 開發(fā)板、通用電源、纜線和軟件
產(chǎn)品目錄頁面: 607 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: EP4SGX230KF40C3N-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230KF40C3-ND - IC STRATIX IV FPGA 230K 1517FBGA
EP4SGX230HF35C3N-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230HF35C3-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3NES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230FF35C3ES-ND - IC STRATIX IV GX 230K 1152-FBGA
EP4SGX230DF29C3NES-ND - IC STRATIX IV GX 230K 780-FBGA
EP4SGX230DF29C3ES-ND - IC STRATIX IV GX 230K 780-FBGA
其它名稱: 544-2594
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
1–22
Switching Characteristics
March 2014
Altera Corporation
Stratix IV Device Handbook
Volume 4: Device Datasheet and Addendum
Inter-transceiver
block skew in Basic
(PMA Direct) ×N
mode (15)
N < 18 channels
located across
three
transceiver
blocks with the
source CMU
PLL located in
the center
transceiver
block
400
400
400
ps
N
18 channels
located across
four transceiver
blocks with the
source CMU
PLL located in
one of the two
center
transceiver
blocks
650
650
650
ps
CMU0 PLL and CMU1 PLL
Supported Data
Range
600
8500
600
6500
600
6375
Mbps
pll_powerdown
minimum pulse
width
(tpll_powerdown)
—1
s
CMU PLL lock time
from
pll_powerdown
de-assertion
100
100
100
s
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 7 of 9)
Symbol/
Description
Conditions
–2 Commercial
Speed Grade
–3 Commercial/
Industrial and
–2× Commercial
Speed Grade (1)
–3 Military (2)
and –4
Commercial/Industrial
Speed Grade
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
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