參數(shù)資料
型號： DDC101U
英文描述： Analog-to-Digital Converter， 20-Bit
中文描述： 模擬到數(shù)字轉(zhuǎn)換器，20位
文件頁數(shù)： 4/28頁
文件大?。?/td> 237K
代理商： DDC101U
DDC101
4
SECTION 2
SPECIFICATIONS
ELECTRICAL
All specifications with unipolar current input range, T
INT
= 1ms, correlated double sampling enabled, System Clock = 2MHz, V
REF
= –2.5V, T
A
= +25
°
C and V
S
=
±
5VDC,
unless otherwise noted.
DDC101
PARAMETER
INPUTS
Charge Input
(6)
Unipolar Input Range
Bipolar Input Range
Input Current
Current Input Range Examples
(10)
Unipolar Input Range
Unipolar Input Range
Bipolar Input Range
Bipolar Input Range
Voltage Input Examples
(10)
Unipolar Input Range
(2)
Bipolar Input Range
(2)
CONDITIONS
MIN
TYP
MAX
UNITS
BTC Output Code
BTC Output Code
Unipolar or Bipolar Range
–1.95
–251.95
500
250
7.8
pC/Integration
pC/Integration
μ
A
T
INT
= 100
μ
s
T
INT
= 1ms
T
INT
= 100
μ
s
T
INT
= 1ms
–0.0195
–1.95
–2.5195
–251.95
5
μ
A
nA
μ
A
nA
500
2.5
250
R
IN
= 10M
, T
INT
= 1ms
R
IN
= 10M
, T
INT
= 1ms
–0.0195
–2.5195
5
V
V
2.5
DYNAMIC CHARACTERISTICS
Conversion Time
Integration Time
System Clock Input
64
64
0.5
256 x 10
6
10
6
2
μ
s
μ
s
MHz
ACCURACY
Unipolar Mode Noise
Noise, Low Level Current Input
(1)
Noise, Low Level Current Input
(1)
Noise, Low Level Current Input
(1)
Noise, Low Level Current Input
(1)
Noise, Voltage Input
(1, 2)
Differential Linearity Error
Unipolar Input Range
C
SENSOR
= 0pF, L = 8
C
SENSOR
= 0pF, L = 1
C
SENSOR
= 100pF, L = 1
C
SENSOR
= 500pF, L = 1
R
IN
≥
20M
0.9
1.6
2.1
4.2
1.9
ppm of FSR, rms
(3)
ppm of FSR, rms
ppm of FSR, rms
ppm of FSR, rms
ppm of FSR, rms
3
Entire Range
0.1% FSR Input
1% FSR Input
10% FSR Input
±
0.005% Reading
±
0.5ppm FSR, max
±
0.00006
±
0.00010
±
0.00055
±
0.0015
% of FSR
% of FSR
% of FSR
% of FSR
Unipolar or Bipolar Input Range
Integral Linearity Error
Unipolar Input Range
(11)
0 to 500 pc/Integration
–1.95 to 0 pc/Integration
0.1% FSR Input
1% FSR Input
10% FSR Input
±
0.0244% Reading
±
2.5ppm FSR, max
±
0.0244% Reading
±
3.0ppm FSR, max
±
0.00028
±
0.00050
±
0.0027
±
0.003
% of FSR
% of FSR
% of FSR
% of FSR
Unipolar or Bipolar Input Range
(11)
No Missing Codes
Unipolar Input Range
Bipolar Input Range
Input Bias Current
DC Gain Error
Output Offset Error
(8)
Input Offset Voltage
(8)
External Voltage Reference, V
REF
Internal Test Signal
Internal Test Signal Accuracy
Gain Sensitivity to V
REF
PSRR
18
16
3
±
0.5
±
0.5
±
0.5
–2.5
100
±
20
1:1
90
Bits
Bits
pA
T
A
= +25
°
C
10
±
2
% of FSR
ppm of FSR
mV
VDC
nA
nA
±
2
V
REF
= 2.5V
±
0.1V
80
dB
PERFORMANCE OVER TEMPERATURE
Output Offset Drift
(8)
Input Offset Voltage Drift
(8)
Input Bias Current Drift
Input Bias Current
Gain Drift
(4)
not including bias current drift
0
1
μ
V/
°
C
μ
V/
°
C
pA/
°
C
pA
ppm/
°
C
+25
°
C to +45
°
C
T
A
= +85
°
C
0.1
8
±
15
0.5
40
DIGITAL INPUT/OUTPUT
Logic Family
Logic Level: V
IH
V
IL
V
OH
V
Data Clock
Data I/O
SETUP Code I/O
(9)
Data Format
Straight Binary
Two’s Complement
TTL Compatible CMOS
I
IH
= +5
μ
A
I
= +5
μ
A
I
OH
= 2 TTL Loads
I
OL
= 2 TTL Loads
+2.0
–0.3
+2.4
0.0
+V
CC
+0.8
+V
CC
0.4
V
V
V
V
8
4
MHz
MHz
Unipolar or Bipolar Range
Unipolar or Bipolar Range
20
21
Bits
Bits
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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