參數(shù)資料
型號(hào)： DDC101U
英文描述： Analog-to-Digital Converter， 20-Bit
中文描述： 模擬到數(shù)字轉(zhuǎn)換器，20位
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 237K
代理商： DDC101U
DDC101
14
constraint is, the voltage that appears at the DDC101 input,
must not exceed 2.5V. If this voltage is exceeded, charge
may be lost and the integration result may be invalid. The
input voltage can be calculated:
maximum input voltage based upon several selections of
input current and input resistor for unipolar input range. The
accuracy of the input resistor will add directly to the DC
Gain Error of the DDC101; the drift of the input resistor will
add directly to the Gain Drift of the DDC101.
Note that the DDC101 output noise decreases as R
in-
creases. This is because the DDC101 noise gain decreases
and the input resistance current noise decreases as R
IN
increases. This effect is shown in the “Noise vs Resistor
Value” typical performance curve.
FIGURE 9b. DDC101 Input Configurations.
i
Input
Resistor
DDC101
R
IN
V
i
DDC101
Data Out
Data Out
Analog Input, pin 3
Analog Common
Analog Input, pin 3
Analog Common
Voltage Input Configuration
Current Input Configuration
L
0.1
0.01
0.001
0.0001
Unipolar Input Level (% of FSR)
0.001
0.01
0.1
1
10
100
FIGURE 10. Maximum Unipolar Integral Linearity Error
Relative to Full-Scale, Converted From % of
Reading Specification.
i(t)
=
C
S
dv
dt
or
1
C
S
therefore,
V
=
i(t)dt
∫
V
=
i
t
C
S
.
The current pulse must occur completely during part of one
DDC101 integration time, and the DDC101 must still have
time to discharge the input capacitance to ground at a
maximum rate of 7.8
μ
A before the DDC101 is triggered
(through the FDS input) to end the integration. In addition,
the total charge integrated must be 500pC or less for the
unipolar range. A current pulse of 100
μ
A for 2
μ
s creates
200pC of charge.
VOLTAGE INPUT SPECIFICATIONS
The DDC101 is a charge digitizing device. With a user
provided input resistor, the DDC101 can digitize voltage
inputs. All of the general charge/current input specifications
apply to the voltage input situation. The specification table
shows the typical noise of the DDC101 including the effects
of a 20M
input resistor, R
IN
.
The input of the DDC101 is a virtual ground. A voltage input
causes a current, i, to flow into the input through R
IN
as
shown in Figure 9b. The maximum input current is deter-
mined by the integration time selected. Table II shows the
V
=
100
μ
A
(
)
2
μ
s
100pF
=
2V.
As an example, with a user supplied input capacitance of
100pF, a current pulse of 100
μ
A for 2
μ
s could be stored
without exceeding 2.5V applied to the input:
INPUT RESISTOR, R
IN
500
μ
s
INTEGRATION TIME
1ms
100
μ
s
Full Scale Input Current
0.5
μ
A
1
μ
A
5
μ
A
Full Scale Voltage
50mV
500mV
5V
50V
100k
1M
10M
100M
50k
500k
5M
50M
10k
100k
1M
10M
TABLE II. Example of Input Resistor Values Unipolar Input
Range.
UNIPOLAR LINEARITY ERRORS
Due to innovative design techniques, the absolute level of
linearity error of the DDC101 improves as the input signal
level decreases when used in the unipolar input mode.
Therefore, in unipolar input mode, the integral linearity of
the DDC101 is specified as a small base error plus a
percentage of reading error or as a percentage of full scale
range. A best-fit straight line method is used to determine
integral linearity. Two different best-fit straight lines are
used for the two unipolar integral linearity specifications.
For bipolar input mode, linearity is specified only as a
percentage of full scale range.
To illustrate the improvement in unipolar mode linearity
error, Figure 10 shows the maximum unipolar integral lin-
earity error (ILE) of the DDC101 as a function of the input
signal level. The maximum integral linearity error is
±
0.0244% of reading
±
2.5ppm of FSR (ILE max for unipo-
lar input of –1.95 to 0 pc is
±
0.0244% of reading
±
3.0ppm
of FSR). Thus, the maximum ILE for an input level of 1%
of FSR is 0.0005%FSR.
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