參數(shù)資料
型號(hào)： DDC101U
英文描述： Analog-to-Digital Converter， 20-Bit
中文描述： 模擬到數(shù)字轉(zhuǎn)換器，20位
文件頁(yè)數(shù)： 18/28頁(yè)
文件大?。?/td> 237K
代理商： DDC101U
DDC101
18
I
FS
1nA
10nA
100nA
1
μ
A
5
μ
A
7.8
μ
A
T
INT
500ms
50ms
5ms
500
μ
s
100
μ
s
64
μ
s
TABLE III. Input Current vs Integration Time Examples
for Maximum Charge. Unipolar input range
maximum charge = 500pC.
±
I
FS
1nA
10nA
100nA
1
μ
A
2.5
μ
A
7.8
μ
A
T
INT
250ms
25ms
2.5ms
250
μ
s
100
μ
s
32
μ
s
TABLE IV. Input Current vs Integration Time Examples
for Maximum Charge. Bipolar input range
maximum charge =
±
250pC.
MULTIPLE INTEGRATIONS
PER CONVERSION CYCLE
If more than 500pC, unipolar (or
±
250pC, bipolar) of charge
must be integrated in one conversion cycle, the DDC101 can
be user programmed for multiple integrations per conversion
cycle. This feature can be used to provide for longer conver-
sion periods for a specific input current other than shown in
the previous table. The integration cycles forming a conver-
sion cycle may be continuous or non-continuous. The num-
ber of integrations per conversion cycle, L, can be 1, 2, 4, 8,
16, 32, 64, 128, or 256. The multiple integrations are
automatically averaged in the DDC101 so that one conver-
sion result is output per total conversion cycle. Note that
each integration requires individual control by the FDS
signal. For example, if L = 4, then four FDS signals per
conversion are required.
FINAL DATA POINT CONFIGURATION LIMITS
In each conversion cycle, the maximum number of final data
points which can be collected is 256. This means that at the
extremes, the DDC101 can be setup to perform one integra-
tion cycle with 256 oversamples, or the DDC101 can be
setup to perform 256 integration cycles with one sample per
integration cycle. The total number of integrations, L, mul-
tiplied by the number of samples per final data point, must
be 256 or less. As an example, if 16 integration cycles, L, are
used, the number of samples per final data point must be 16
or less.
NOTE: When CDS is used, the initial data points impose no
additional conversion sampling limitations.
FREQUENCY RESPONSE
The DDC101 charge digitizing A/D Converter is a sampled
system whose frequency response has three separate compo-
nents. These components are multiplied together to make the
total frequency characteristic of the DDC101. The three
frequency response components are shown below. Each
INTEGRATIONS
PER CONVERSION
CONVERSION
TIME
MAX CHARGE/
CONVERSION
I
FS
L = 1
L = 2
L = 4
L = 8
L = 16
L = 32
L = 64
L = 128
L = 256
10nA
10nA
10nA
10nA
10nA
10nA
10nA
10nA
10nA
50ms
100ms
200ms
400ms
800ms
1.6s
3.2s
6.4s
12.8s
500pC
1000pC
2000pC
4000pC
8000pC
16000pC
32000pC
64000pC
128000pC
TABLE V. Integrations/Conversion vs Conversion Time.
Example for multiple integrations with unipolar
input range.
FIGURE 15. Conversion Cycle with Two Integrations.
Conversion Cycle
Integration 1
Integration 2
CDAC
Charge
One data output per
conversion cycle with
two integrations/conversion
Time
individual component has a sinc (sinx/x) frequency response
function.
1. Basic Integration
This is the characteristic sin(x)/x response of the basic
integration function. This response is controlled by the
measurement time of the DDC101, T
MEAS
; see Figure 16.
2. Oversampling
This is the low pass filter characteristic of the digital
filter’s oversampling. This response reduces the broad-
band noise in the input signal of the DDC101. Broadband
noise decreases as the number of oversamples increases.
This response is controlled by the number of oversamples,
M; see Figure 17.
3. Multiple Integrations
This is the low pass filter characteristic that results when
the digital filter is used to average multiple integrations.
This will determine the primary response of the DDC101
if two or more integrations are internally averaged. This
response is controlled by the total conversion time of the
DDC101; see Figure 18.
Input frequencies are multiplied by the DDC101 frequency
response. The Nyquist frequency is f
/2, where f
is
the DDC101 conversion rate. The highest frequency that can
be reconstructed from the output data is f
/2. Input
frequencies above Nyquist are multiplied by the DDC101
frequency response and are then aliased into DC to f
CONV
/2.
相關(guān)PDF資料
PDF描述
DDC114 Quad Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
DDC114TH-7 NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR
DDC114EK NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
DDC114TH NPN PRE-BIASED SMALL SIGNAL SOT-563 DUAL SURFACE MOUNT TRANSISTOR
DDC114TK NPN PRE-BIASED SMALL SIGNAL SOT-26 DUAL SURFACE MOUNT TRANSISTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DDC101UG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 20-Bit Anlg-to-Dig Converter RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
DDC1021 制造商:MPSIND 制造商全稱:MPS Industries, Inc. 功能描述:3W, Wide Input Range SMD, Single & Dual Output DC/DC Converters
DDC1022 制造商:MPSIND 制造商全稱:MPS Industries, Inc. 功能描述:3W, Wide Input Range SMD, Single & Dual Output DC/DC Converters
DDC1023 制造商:MPSIND 制造商全稱:MPS Industries, Inc. 功能描述:3W, Wide Input Range SMD, Single & Dual Output DC/DC Converters
DDC1024 制造商:MPSIND 制造商全稱:MPS Industries, Inc. 功能描述:3W, Wide Input Range SMD, Single & Dual Output DC/DC Converters
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*