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參數(shù)資料
| 型號(hào)： | DAC8143 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Serial Daisy-Chain CMOS D/A Converter(12位串行菊花鏈D/A轉(zhuǎn)換器) |
| 中文描述： | 12位串行菊花鏈的CMOS D / A轉(zhuǎn)換（12位串行菊花鏈的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 319K |
| 代理商： | DAC8143 |
DAC8143
–13–
REV. B
Figure 10. Multiple DAC8143s with 3-Wire Interface
Figure 11. Analog/Digital Divider
ANALOG/DIGIT AL DIVISION
T he transfer function for the DAC8143 connect in the multiply-
ing mode as shown in Figures 7 and 8 is:
V
O
= –
V
IN
A
1
2
1
+
A
2
2
2
+
A
3
2
3
+
...
A
12
2
12
where A
X
assumes a value of 1 for an “ON” bit and 0 for an
“OFF” bit.
T he transfer function is modified when the DAC is connected in
the feedback of an operational amplifier as shown in Figure 11
and is:
V
O
=
±
V
IN
2
3
+
...
A
12
A
1
2
1
+
A
2
2
2
+
A
3
2
12
T he above transfer function is the division of an analog voltage
(V
REF
) by a digital word. T he amplifier goes to the rails with all
bits “OFF” since division by zero is infinity. With all bits “ON”
the gain is 1 (
±
1 LSB). T he gain becomes 4096 with the LSB,
Bit 12, “ON”.
APPLICAT ION T IPS
In most applications, linearity depends upon the potential of
I
OUT 1,
I
OUT 2,
and AGND (Pins 1, 2 and 3) being exactly equal
to each other. In most applications, the DAC is connected to an
external op amp with its noninverting input tied to ground (see
Figures 7 and 8). T he amplifier selected should have a low input
bias current and low drift over temperature. T he amplifier’s in-
put offset voltage should be nulled to less than
±
200
μ
V (less
than 10% of 1 LSB).
T he operational amplifier’s noninverting input should have a
minimum resistance connection to ground; the usual bias cur-
rent compensation resistor should not be used. T his resistor can
cause a variable offset voltage appearing as a varying output er-
ror. All grounded pins should tie to a single common ground
point, avoiding ground loops. T he V
DD
power supply should
have a low noise level with no transients greater than +17 V.
It is recommended that the digital inputs be taken to ground or
V
DD
via a high value (1 M
) resistor; this will prevent the accu-
mulation of static charge if the PC card is disconnected from the
system.
Peak supply current flows as the digital input pass through the
transition region (see the Supply Current vs. Logic Input Volt-
age graph under the T ypical Performance Characteristics). T he
supply current decreases as the input voltage approaches the
supply rails (V
DD
or DGND), i.e., rapidly slewing logic signals
that settle very near the supply rails will minimize supply current.
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