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參數(shù)資料
| 型號： | DAC8143 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Serial Daisy-Chain CMOS D/A Converter(12位串行菊花鏈D/A轉(zhuǎn)換器) |
| 中文描述： | 12位串行菊花鏈的CMOS D / A轉(zhuǎn)換（12位串行菊花鏈的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 319K |
| 代理商： | DAC8143 |
DAC8143
–10–
REV. B
T able I. DAC8143 T ruth T able
DAC8143 Logic Inputs
Input Register/
Digital Output
ST B
4
ST B
3
Control Inputs
ST B
2
DAC Register
CLR
Control Inputs
LD
2
ST B
1
LD
1
DAC8143 Operation
Notes
0
0
0
g
1
1
f
1
0
g
0
0
g
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
Serial Data Bit Loaded from SRI
into Input Register and Digital Output
(SRO Pin) after 12 Clocked Bits.
2, 3
1
X
X
X
X
0
X
X
X
X
1
X
X
X
X
1
No Operation (Input Register and SRO)
3
Reset DAC Register to Zero Code
(Code: 0000 0000 0000)
(Asynchronous Operation)
0
X
X
1, 3
1
1
1
X
X
1
No Operation (DAC Register and SRO)
3
1
0
0
Load DAC Register with the Contents
of Input Register
3
NOT ES
1
CLR
= 0 asynchronously resets DAC Register to 0000 0000 0000, but has no effect on Input Register.
2
Serial data is loaded into Input Register MSB first, on edges shown.
g
is positive edge,
f
is negative edge.
3
0 = Logic LOW, 1 = Logic HIGH, X = Don’t Care.
Serial data is clocked into the input register and buffered output
stage with ST B
1
, ST B
2
, or ST B
4
. T he strobe inputs are active
on the rising edge. ST B
3
may be used with a falling edge clock
data.
Serial data output (SRO) follows the serial data input (SRI) by
12 clocked bits.
Holding any ST ROBE input at its selected state (i.e., ST B
1
,
ST B
2
or ST B
4
at logic HIGH or ST B
3
at logic LOW) will act to
prevent any further data input.
When a new data word has been entered into the input register,
it is transferred to the DAC register by asserting both LOAD
inputs.
T he
CLR
input allows asynchronous resetting of the DAC regis-
ter to 0000 0000 0000. T his reset does not affect data held in
the input registers. While in unipolar mode, a CLEAR will re-
sult in the analog output going to 0 V. In bipolar mode, the out-
put will go to –V
REF
.
INT E RFACE INPUT DE SCRIPT ION
ST B
1
(Pin 4), ST B
2
(Pin 8), ST B
4
(Pin 11)—Input Register
and Buffered Output Strobe. Inputs Active on Rising
E dge.
Selected to load serial data into input register and buff-
ered output stage. See T able I for details.
ST B
3
(Pin 10)—Input Register and Buffered Output
Strobe Input. Active on Falling E dge.
Selected to load serial
data into input register and buffered output stage. See T able I
for details.
LD
1
(Pin 5), LD
2
(Pin 9)—Load DAC Register Inputs. Ac-
tive Low.
Selected together to load contents of input register
into DAC register.
CLR
(Pin 13)—Clear Input. Active Low. Asynchronous.
When LOW, 12-bit DAC register is forced to a zero code (0000
0000 0000) regardless of other interface inputs.
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