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參數(shù)資料
| 型號： | DAC8143 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit Serial Daisy-Chain CMOS D/A Converter(12位串行菊花鏈D/A轉(zhuǎn)換器) |
| 中文描述： | 12位串行菊花鏈的CMOS D / A轉(zhuǎn)換（12位串行菊花鏈的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 319K |
| 代理商： | DAC8143 |
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
12-Bit Serial Daisy-Chain
CMOS D/AConverter
DAC8143
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Fast, Flexible, Microprocessor Interfacing in Serially
Controlled Systems
Buffered Digital Output-Pin for Daisy-Chaining
Multiple DACs
Minimizes Address-Decoding in Multiple DAC
Systems—Three Wire Interface for Any Number of DACs
One Data Line
One CLK Line
One Load Line
Improved Resistance to ESD
–40
8
C to +85
8
C for the Extended Industrial Temperature
Range
Available in Die Form
APPLICATIONS
Multiple-Channel Data Acquisition Systems
Process Control and Industrial Automation
Test Equipment
Remote Microprocessor-Controlled Systems
GE NE RAL INFORMAT ION
T he DAC8143 is a 12-bit serial-input daisy-chain CMOS D/A
converter, which features serial data input and buffered serial
data output. It was designed for multiple serial DAC systems,
where serially daisy-chaining one DAC after another is greatly
simplified.
T he DAC8143 also minimizes address decoding lines enabling
simpler logic interfacing. It allows 3-wire interface for any num-
ber of DACs: one data line, one CLK line, and one load line.
Serial data in the input register (MSB first) is sequentially
clocked out to the SRO pin as the new data word (MSB first) is
simultaneously clocked in from the SRI pin. T he strobe inputs
are used to clock in/out data on the rising or falling (user
selected) strobe edges (ST B
1
, ST B
2
,
ST B
3
,
ST B
4
).
When the shift register's data has been updated, the new data
word is transferred to the DAC register with use of
LD
1
and
LD
2
inputs.
Separate LOAD control inputs allow simultaneous output up-
dating of multiple DACs. An asynchronous CLEAR input re-
sets the DAC register without altering data in the input register.
Improved linearity and gain error performance permits reduced
circuit parts count through the elimination of trimming compo-
nents. Also, fast interface timing reduces timing design consid-
eration while minimizing microprocessor wait states.
FUNCT IONAL BLOCK DIAGRAM
12-BIT
D/A CONVERTER
INPUT 12-BIT
SHIFT REGISTER
IN
OUT
CLK
LOAD
DAC REGISTER
DAC8143
15
13
5
9
4
10
11
8
7
12
6
3
2
1
16
14
DGND
V
REF
CLR
LD
1
LD
2
STB
1
STB
4
STB
3
STB
2
V
DD
SRI
R
FB
I
OUT1
I
OUT2
AGND
SRO
T he DAC8143 is available in standard cerdip and plastic pack-
ages that are compatible with auto-insertion equipment.
Cerdip and plastic packages devices come in the extended in-
dustrial temperature range of –40
°
C to +85
°
C.
MULT IPLE DAC8143s WIT H 3-WIRE INT E RFACE
STROBE
DAC8143
LOAD
SRI
SRO
ADDRESS
DECODER
ADDRESS BUS
STROBE
DAC8143
LOAD
SRI
SRO
STROBE
DAC8143
LOAD
SRI
SRO
STROBE
DAC8143
LOAD
SRI
SRO
WR
DB
X
μP
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