參數(shù)資料
型號: DAC8143
廠商: Analog Devices, Inc.
英文描述: 12-Bit Serial Daisy-Chain CMOS D/A Converter(12位串行菊花鏈D/A轉(zhuǎn)換器)
中文描述: 12位串行菊花鏈的CMOS D / A轉(zhuǎn)換(12位串行菊花鏈的D / A轉(zhuǎn)換器)
文件頁數(shù): 12/16頁
文件大小: 319K
代理商: DAC8143
DAC8143
–12–
REV. B
Figure 9. Bipolar Operation (4-Quadrant, Offset Binary)
BIPOLAR OPE RAT ION (4-QUADRANT )
Figure 9 details a suggested circuit for bipolar, or offset binary
operation. T able III shows the digital input-to-analog output re-
lationship. T he circuit uses offset binary coding. T wo’s comple-
ment code can be converted to offset binary by software
inversion of the MSB or by the addition of an external inverter
to the MSB input.
Resistor R3, R4, and R5 must be selected to match within
0.01% and must all be of the same (preferably metal foil) type
to assure temperature coefficient match. Mismatching between
R3 and R4 causes offset and full-scale error.
Calibration is performed by loading the DAC register with 1000
0000 0000 and adjusting R1 until V
OUT
= 0 V. R1 and R2 may
be omitted by adjusting the ratio of R3 to R4 to yield V
OUT
=
0 V. Full scale can be adjusted by loading the DAC register with
1111 1111 1111 and adjusting either the amplitude of V
REF
or
the value of R5 until the desired V
OUT
is achieved.
DAISY -CHAINING DAC8143s
Many applications use multiple serial-input DACs that use nu-
merous interconnecting lines for address decoding and data
lines. In addition, they use some type of buffering to reduce
loading on the bus. T he DAC8143 is ideal for just such an ap-
plication. It not only reduces the number of inter-connecting
lines, but also reduces bus loading. T he DAC8143 can be daisy-
chained with only three lines: one data line, one CLK line, and
one Load line, see Figure 10.
T able III. Bipolar (Offset Binary) Code T able
Digital Input
MSB
Nominal Analog Output
(V
OUT
as shown in Figure 9)
LSB
1 1 1 1 1 1 1 1 1 1 1 1
+
V
REF
2047
2048
1
2048
1 0 0 0 0 0 0 0 0 0 0 1
+
V
REF
1 0 0 0 0 0 0 0 0 0 0 0
0
0 1 1 1 1 1 1 1 1 1 1 1
V
REF
1
2048
2047
2048
2048
2048
0 0 0 0 0 0 0 0 0 0 0 1
V
REF
0 0 0 0 0 0 0 0 0 0 0 0
V
REF
NOT ES
1
Nominal full scale for the circuits of Figure 9 is given by
2047
2048
FS
=
V
REF
.
2
Nominal LSB magnitude for the circuits of Figure 9 is given by
.
LSB
=
V
REF
1
2048
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