參數(shù)資料
型號： DAC5573IWR
廠商： Texas Instruments, Inc.
英文描述： QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER
中文描述： 四，8位，低功耗，電壓輸出，接口數(shù)字，模擬轉(zhuǎn)換器
文件頁數(shù)： 22/30頁
文件大小： 499K
代理商： DAC5573IWR
www.ti.com
Master Receiver Reading From a Slave Transmitter (DAC5573) in Standard/Fast Modes
When reading data back from the DAC5573, the user begins with an address byte (with R/W = 0) after which the
DAC5573 acknowledges by pulling SDA low. This address byte is usually followed by the control byte, which is
also acknowledged by the DAC5573. Following this there is a REPEATED START condition by the master and
the address is resent with (R/W = 1). This is acknowledged by the DAC5573, indicating that it is prepared to
transmit data. Two or three bytes of data are then read back from the DAC5573, depending on the (PD0-Bit).
The value of
Buff-Sel1
and
Buff-Sel0
determines, which channel data is read back. A STOP condition follows.
DAC5573
SLAS401–NOVEMBER 2003
With the (PD0-Bit = 0) the DAC5573 transmits 2 bytes of data,
HIGH-BYTE
followed by the
LOW-BYTE
(refer to
Table 6. Data Readback Mode - 2 bytes).
With the (PD0-Bit = 1) the DAC5573 transmits 3 bytes of data,
POWER-DOWN-BYTE
followed by the
HIGH-BYTE
followed by the
LOW-BYTE
(refer to Table 6. Data Readback Mode - 3 bytes).
Table 6. Read Sequence in F/S Mode
DATA READBACK MODE - 2 BYTES
Transmitter
MSB
Master
Master
1
DAC5573
Master
A3
DAC5573
Master
Master
1
DAC5573
DAC5573
D7
Master
DAC5573
x
Master
Master
DATA READBACK MODE - 3 BYTES
Transmitter
MSB
Master
Master
1
DAC5573
Master
A3
DAC5573
Master
Master
1
DAC5573
DAC5573
PD1
Master
DAC5573
D7
Master
DAC5573
x
Master
Master
6
5
4
3
2
1
LSB
Comment
Begin sequence
Write addressing (
R/W=0
)
Start
0
0
1
1
A1
A0
R/W
DAC5573 acknowledges
Load 0
DAC5573 acknowledges
Repeated start
1
DAC5573 acknowledges
D4
Master acknowledges
x
Master not acknowledges
Stop or repeated start
(1)
A2
Load 1
x
Buff Sel 1
Buff Sel 0
PD0
Control byte (
PD0=0
)
0
0
1
A1
A0
R/W
Read addressing (
R/W = 1
)
D6
D5
D3
D2
D1
D0
Reading data word, high byte
x
x
x
x
x
x
Reading data word, low byte
Master signal end of read
Done
6
5
4
3
2
1
LSB
Comment
Begin sequence
Write addressing (
R/W=0
)
Start
0
0
1
1
A1
A0
R/W
DAC5573 acknowledges
Load 0
DAC5573 acknowledges
Repeated start
1
DAC5573 acknowledges
1
Master acknowledges
D4
Master acknowledges
x
Master not acknowledges
Stop or repeated start
(1)
A2
Load 1
x
Buff Sel 1
Buff Sel 0
PD0
Control byte (
PD0=1
)
0
0
1
A1
A0
R/W
Read addressing (
R/W = 1
)
PD2
1
1
1
1
1
Read power down byte
D6
D5
D3
D2
D1
D0
Reading data word, high byte
x
x
x
x
x
x
Reading data word, low byte
Master signal end of read
Done
(1)
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
22
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