參數(shù)資料
型號: DAC5573IWR
廠商: Texas Instruments, Inc.
英文描述: QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER
中文描述: 四,8位,低功耗,電壓輸出,接口數(shù)字,模擬轉(zhuǎn)換器
文件頁數(shù): 16/30頁
文件大?。?/td> 499K
代理商: DAC5573IWR
www.ti.com
Most Significant Byte
Most significant byte MSB[7:0] consists of eight most significant bits of 8-bit unsigned binary D/A conversion
data. C0=1, MSB[7], MSB[6] indicate a power-down operation as shown in Table 8.
Least Significant Byte
Least significant byte LSB[7:0] consists of the 8
don't care
bits. DAC5573 updates at the falling edge of the
acknowledge signal that follows the LSB[0] bit. Therefore, the LS byte is needed for the update to occur.
Default Readback Condition
If the user initiates a readback of a specified channel without first writing data to that specified channel, the
default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase.
DAC5573
SLAS401–NOVEMBER 2003
Table 2. Control Byte
C7
C6
C5
C4
C3
Don't
Care
C2
C1
C0
MSB7
MSB
(PD1)
MSB6
MSB-1
(PD2)
MSB5...
A3
A2
Load1
Load0
Ch Sel 1
Ch Sel 0
PD0
MSB-2 ...LSB
DESCRIPTION
(Address
Select)
(A3 and A2
should corre-
spond to the
package ad-
dress, set via
pins A3 and
A2)
0
0
X
0
0
0
Data
Write to temporary
register A (TRA) with
data
Write to temporary
register B (TRB) with
data
Write to temporary
register C (TRC) with
data
Write to temporary
register D (TRD) with
data
Write to TRx (selected
by C2 &C1
w/Powerdown Command
Write to TRx (selected
by C2 &C1 and load
DACx w/data
Power-down DACx
(selected by C2 and C1)
Write to TRx (selected
by C2 &C1 w/ data and
load all DACs
Power-down DACx
(selected by C2 and C1)
& load all DACs
0
0
X
0
1
0
Data
0
0
X
1
0
0
Data
0
0
X
1
1
0
Data
(00, 01, 10, or 11)
0
0
X
1
See Table 8
0
(00, 01, 10, or 11)
0
1
X
0
Data
(00, 01, 10, or 11)
0
1
X
1
See Table 8
0
(00, 01, 10, or 11)
1
0
X
0
Data
(00, 01, 10, or 11)
1
0
X
1
See Table 8
0
Broadcast Modes (controls up to 4 devices on a single serial bus)
Update all DACs, all
devices with previously
stored TRx data
Update all DACs, all
devices with MSB[7:0]
and LSB[7:0] data
Power-down all DACs,
all devices
X
X
1
1
X
0
X
X
X
X
X
1
1
X
1
X
0
Data
X
X
1
1
X
1
X
1
See Table 8
0
16
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