參數(shù)資料
型號(hào)： DAC5573IWR
廠(chǎng)商： Texas Instruments, Inc.
英文描述： QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER
中文描述： 四，8位，低功耗，電壓輸出，接口數(shù)字，模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 11/30頁(yè)
文件大?。?/td> 499K
代理商： DAC5573IWR
www.ti.com
THEORY OF OPERATION
D/A SECTION
The architecture of the DAC5573 consists of a string DAC followed by an output buffer amplifier. Figure 27
shows a generalized block diagram of the DAC architecture.
_
+
Resistor String
Ref
Ref+
DAC Register
V
OUT
50 k
50 k
V
REF
H
V
REF
L
70 k
V
OUT
2
V
REF
L
(
V
REF
H
V
REF
L
)
D
256
RESISTOR STRING
The resistor string section is shown in Figure 28. It is basically a divide-by-2 resistor, followed by a string of
resistors, each of value R. The code loaded into the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the
amplifier. Because the architecture consists of a string of resistors, it is specified monotonic.
V
REF
H
To Output
Amplifier
R
R
R
R
V
REF
L
Output Amplifier
The output buffer is a gain-of-2 noninverting amplifier, capable of generating rail-to-rail voltages on its output,
which gives an output range of 0V to V
DD
. It is capable of driving a load of 2 k
in parallel with 1000 pF to GND.
The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/μs
with a half-scale settling time of 8 μs with the output unloaded.
I
2
C Interface
I
2
C is a 2-wire serial interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus
is
idle
, both SDA and SCL lines are pulled high. All the I
2
C-compatible devices connect to the I
2
C bus through
open drain I/O pins, SDA and SCL. A
master
device, usually a microcontroller or a digital signal processor,
controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also
generates specific conditions that indicate the START and STOP of data transfer. A
slave
device receives and/or
transmits data on the bus under control of the master device.
DAC5573
SLAS401–NOVEMBER 2003
Figure 27. R-String DAC Architecture
The input coding to the DAC5573 is unsigned binary, which gives the ideal output voltage as:
Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255.
Figure 28. Typical Resistor String
11
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