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參數(shù)資料
| 型號： | DAC5573IWR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 四，8位，低功耗，電壓輸出，接口數(shù)字，模擬轉換器 |
| 文件頁數(shù)： | 14/30頁 |
| 文件大小： | 499K |
| 代理商： | DAC5573IWR |
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DAC5573 I
2
C Update Sequence
The DAC5573 requires a start condition, a valid I
2
C address, a control byte, an MSB byte, and an LSB byte for a
single update. After the receipt of each byte, DAC5573 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I
2
C address selects the DAC5573. The control byte sets the operational
mode of the selected DAC5573. Once the operational mode is selected by the control byte, DAC5573 expects an
MSB byte followed by an LSB byte for data update to occur. DAC5573 performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
Address Byte
Broadcast Address Byte
DAC5573
SLAS401–NOVEMBER 2003
The control byte needs not to be resent until a change in operational mode is required. The bits of the control
byte continuously determine the type of update performed. Thus, for the first update, DAC5573 requires a start
condition, a valid I
2
C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,
DAC5573 needs an MSB byte, and an LSB byte as long as the control command remains the same. MSB byte
contains DAC data LSB byte contains 8
don't care
bits.
Using the I
2
C high-speed mode (f
scl
= 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DAC update other than
the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge
signal), at 188.88 kSPS. Using the fast mode (f
= 400 kHz), clock running at 400 kHz, maximum DAC update
rate is limited to 22.22 kSPS. Once a stop condition is received, DAC5573 releases the I
2
C bus and awaits a
new start condition.
MSB
1
LSB
R/W
0
0
1
1
A1
A0
The address byte is the first byte received following the START condition from the master device. The first five
bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select
bits A1 and A0. The A1, A0 address inputs can be connected to V
DD
or digital GND, or can be actively driven by
TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of
the DAC5573. Up to 16 devices (DAC5573) can still be connected to the same I
2
C-bus.
MSB
1
LSB
0
0
0
1
0
0
0
Broadcast addressing is also supported by DAC5573. Broadcast addressing can be used for synchronously
updating or powering down multiple DAC5573 devices. DAC5573 is designed to work with other members of the
DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address,
DAC5573 responds regardless of the states of the address pins. Broadcast is supported only in write mode
(master writes to DAC5573).
14
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DAC5574 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL TO ANALOG CONVERTER |
| DAC5574EVM | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 DAC5574 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| DAC5574IDGS | 功能描述:數(shù)模轉換器- DAC 8-bit Quad Converter with I2C interface RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC5574IDGS | 制造商:Texas Instruments 功能描述:IC DAC 8BIT 188KSPS MSOP-10 |
| DAC5574IDGSG4 | 功能描述:數(shù)模轉換器- DAC 8-bit Quad Converter with I2C interface RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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