參數(shù)資料
型號(hào)： DAC1005D750HW
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 外設(shè)及接口
英文描述： Dual 10-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
封裝： DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6
文件頁(yè)數(shù)： 24/42頁(yè)
文件大?。?/td> 353K
代理商： DAC1005D750HW
DAC1005D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
24 of 42
NXP Semiconductors
DAC1005D750
Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating
10.4 Input clock
The DAC1005D750 can operate at the following clock frequencies:
PLL on:
up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode
PLL off:
up to 750 MHz
The input clock is LVDS compliant (see
Figure 8
) but it can also be interfaced with CML
differential sine wave signal (see
Figure 9
).
10.5 Timing
The DAC1005D750 can operate at a sampling frequency (f
s
) up to 750 Msps with an input
data rate (f
data
) up to 185 MHz. When using the internal PLL, the input data is referenced
to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a
reference. The input timing in the second case is shown in
Figure 10
.
Fig 8.
LVDS clock configuration
Fig 9.
Interfacing CML to LVDS
001aah021
100
Ω
LVDS
CLKINP
CLKINN
LVDS
Z
diff
= 100
Ω
001aah020
55
Ω
55
Ω
1.1 k
Ω
2.2 k
Ω
100 nF
CML
100 nF
100 nF
CLKINP
LVDS
CLKINN
AGND
V
DDA(1V8)
1 k
Ω
Z
diff = 100
Ω
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DAC1005D750HW/C1,5 功能描述:數(shù)模轉(zhuǎn)換器- DAC DUAL 10BITS DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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