參數(shù)資料
型號: DA28F016SA-120
廠商: INTEL CORP
元件分類: DRAM
英文描述: 28F016SA 16-MBIT (1 MBIT X 16, 2 MBIT X 8)FlashFile MEMORY
中文描述: 1M X 16 FLASH 12V PROM, 120 ns, PDSO56
封裝: 23.70 X 16 MM, 1.80 MM HEIGHT, SSOP-56
文件頁數(shù): 48/63頁
文件大?。?/td> 635K
代理商: DA28F016SA-120
28F016SV FlashFile MEMORY
E
48
V
V
WE# (W)
OE# (G)
RP# (P)
V
PP
CEx # (E)
(V)
DEEP
POWER-DOWN
IH
IL
V
V
IH
IL
V
V
IH
IL
ADDRESSES (A)
t
AVAV
t
WHAX
t
WHEH
ELWL
t
tWHDX
WHWL
t
V
V
IH
IL
t
WLWH
tDVWH
V
IH
IL
V
V
IH
V
IL
PHWL
t
HIGH Z
IN
D
D
IN
IN
A
t
t
QVVL2
D
IN
IL
V
PPH2
V
PPLK
V
t
VPWH2
READ EXTENDED
STATUS REGISTER DATA
DATA (D/Q)
WHQV1,2
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VALID ADDRESS
E& DATA (DATA-WRITE) OR
AUTOMATED DATA-WRITE
OR ERASE DELAY
V
V
RY/BY# (R)
t
WHRL
t
WHGL
OH
OL
V
V
IH
IL
ADDRESSES (A)
t
AVAV
AVWH
t
t
WHAX
IN
A
READ COMPATIBLE
STATUS REGISTER DATA
D
IN
REGISTER COMMAND
A=RA
NOTE 1
NOTE 2
NOTE 3
NOTE 4
DOUT
AVWH
t
t
RHPL
t
GHWL
NOTE 5
PPH1
V
NOTE 7
NOTE 6
t
VPWH1
tQVVL1
0528_15
NOTES:
1. This address string depicts data program/erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/erase operations.
4. CE
X
# is defined as the latter of CE
0
# or CE
1
# going low or the first of CE
0
# or CE
1
# going high.
5. RP# low transition is only to show t
RHPL
; not valid for above read and program cycles.
6. V
PP
voltage during program/erase operations valid at both 12V and 5V.
7. V
PP
voltage equal to or below V
PPLK
provides complete flash memory array protection.
Figure 15. AC Waveforms for Command Write Operations
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