12 FN6785.0 July 29, 2010 43 IREF I - Overcurrent reference analog input. Used in setting the overcurrent error detect exter" />
參數(shù)資料
型號(hào)： D2-45057-QR-T
廠商： Intersil
文件頁(yè)數(shù)： 4/31頁(yè)
文件大小： 0K
描述： IC DGTL AMP PWM CTRLR 68QFN
標(biāo)準(zhǔn)包裝： 3,000
系列： D2Audio™
類型： D 類
輸出類型： 2 通道（立體聲）
在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： 30W x 1 @ 8 歐姆
電源電壓： 9 V ~ 26 V
安裝類型： 表面貼裝
供應(yīng)商設(shè)備封裝： 68-QFN 裸露焊盤（10x10）
封裝/外殼： 68-VFQFN 裸露焊盤
包裝： 帶卷 (TR)
D2-45057, D2-45157
12
FN6785.0
July 29, 2010
43
IREF
I
-
Overcurrent reference analog input. Used in setting the overcurrent error detect externally-
set threshold. The pin needs to be connected to a 100kΩ resistor to ground to set the
overcurrent threshold according to the specified limits.
44
VDDHV
P
+HV
High Voltage internal driver supply power. All of the HVDD[A:D] pins and the VDDHV pin
connect to the system “HV” power source. The internal +5V supply regulators also operate
from this VDDHV input.
45
REG5V
P
5
5V internal regulator filter connect. A +5V supply is internally generated from the voltage
source provided at the VDD pin. REG5V is used for external connection of a decoupling
capacitor.
46
HVDDB
P
HV
Output stage B high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
47
HGNDB
GND
HV
Output stage B high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
48
OUTB
O
HV
PWM power amplifier output, channel B.
49
HSBSB
I
HV
High-side boot strap input, output channel B. Capacitor couples to OUTB amplifier output.
50
HSBSA
I
HV
High-side boot strap input, output channel A. Capacitor couples to OUTA amplifier output.
51
OUTA
O
HV
PWM power amplifier output, channel A.
52
HGNDA
GND
HV
Output stage A high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
53
HVDDA
P
HV
Output stage A high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
54
nPDN
I
3.3
Power-down and mute input. Active low. When this input is low, all 4 outputs become
inactive and their output stages float, and their output is muted. Internal logic and other
references remain active during this power-down state.
55
LINER
O
3.3
“Right” channel PWM output, with 16mA drive strength. Connects to filter network for
supplying line-level analog output.
56
LINEL
O
3.3
“Left” channel PWM output, with 16mA drive strength. Connects to filter network for
supplying line-level analog output.
57
OCFG1
I
3.3
Output configuration control select. OCFG0 and OCFG1 are logic inputs to select the output
configuration mode of the output stages. Connects to either PWMGND ground or PWMVDD
(+3.3V) through nominal 10kΩ resistor to select output configuration.
58
OCFG0
I
3.3
Output configuration control select. OCFG0 and OCFG1 are logic inputs to select the output
configuration mode of the output stages. Connects to either PWMGND ground or PWMVDD
(+3.3V) through nominal 10kΩ resistor to select output configuration.
59
PWMGND
P
3.3
PWM output pin ground. Internally connected to RGND.
60
PWMVDD
P
3.3
PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally
connected to RVDD.
61
PLLGND
P
1.8
PLL Analog ground. Should be tied to low voltage ground (CGND, RGND) through single
point connection to isolate ground noise on board and minimizing affecting of PLL.
62
XTALI
P
1.8
Crystal oscillator analog input port.
63
XTALO
P
1.8
Crystal oscillator analog output port. (This output drives the crystal and XTALO does not
have a drive strength specification.)
64
PLLVDD
P
1.8
PLL Analog power, 1.8V.
Pin Description (Continued)
PIN
NAME
(Note 13) TYPE
VOLTAGE
LEVEL
(V)
DESCRIPTION
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