11 FN6785.0 July 29, 2010 24 nERROR/ CFG0 I/O 3.3 Output configuration selection input, and nERROR output. Upon device reset" />
參數資料
型號: D2-45057-QR-T
廠商: Intersil
文件頁數: 3/31頁
文件大小: 0K
描述: IC DGTL AMP PWM CTRLR 68QFN
標準包裝: 3,000
系列: D2Audio™
類型: D 類
輸出類型: 2 通道(立體聲)
在某負載時最大輸出功率 x 通道數量: 30W x 1 @ 8 歐姆
電源電壓: 9 V ~ 26 V
安裝類型: 表面貼裝
供應商設備封裝: 68-QFN 裸露焊盤(10x10)
封裝/外殼: 68-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
D2-45057, D2-45157
11
FN6785.0
July 29, 2010
24
nERROR/
CFG0
I/O
3.3
Output configuration selection input, and nERROR output. Upon device reset, pin operates
as input, using application-installed pull-up or pull-down connection to pin to specify one of
4 amplifier configurations. Upon internal D2-45057, D2-45157 firmware execution, pin
becomes output, providing active-low output drive when amplifier protection monitoring
detects an error condition. When operating as output, provides 4mA drive strength. (Note:
This pin may also be referenced as “PSCURR” on some reference designs. Function is
identical regardless of name.)
25
PSSYNC/
CFG1
I/O
3.3
Output configuration selection input, and power supply sync output. Upon device reset, pin
operates as input, using application-installed pull-up or pull-down connection to pin to
specify one of 4 amplifier configurations. Upon internal D2-45057, D2-45157 firmware
execution, pin becomes output, providing synchronizing signal to on-board power supply
circuits. When operating as output, provides 4mA drive strength. Note: This pin may also
be referenced as “PSTEMP” on some reference designs. Function is identical regardless of
name.
26 PROTECT0
I/O
3.3
PWM protection input. Input has hysteresis. Protection monitoring functionality of pin is
controlled by internal D2-45057, D2-45157 firmware, and dependent on which of the 4
amplifier configurations is enabled.
27 PROTECT1
I/O
3.3
PWM protection input. Input has hysteresis. Protection monitoring functionality of pin is
controlled by internal D2-45057, D2-45157 firmware, and dependent on which of the 4
amplifier configurations is enabled.
28 PROTECT2
I/O
3.3
PWM protection input. Input has hysteresis. Protection monitoring functionality of pin is
controlled by internal D2-45057, D2-45157 firmware, and dependent on which of the 4
amplifier configurations is enabled.
29
nERROR0
O
3.3
Overcurrent protection output, channel A output stage. Open drain 16mA driver, with internal
100kΩ (approx.) pull-up. Pulls low when active from overcurrent detection of output stage.
30
nERROR1
O
3.3
Overcurrent protection output, channel B output stage. Open drain 16mA driver, with internal
100kΩ (approx.) pull-up. Pulls low when active from overcurrent detection of output stage.
31
nERROR2
O
3.3
Overcurrent protection output, channel C output stage. Open drain 16mA driver, with internal
100kΩ (approx.) pull-up. Pulls low when active from overcurrent detection of output stage.
32
nERROR3
O
3.3
Overcurrent protection output, channel D output stage. Open drain 16mA driver, with internal
100kΩ (approx.) pull-up. Pulls low when active from overcurrent detection of output stage.
33
HVDDD
P
HV
Output stage D high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
34
HGNDD
GND
HV
Output stage D high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
35
OUTD
O
HV
PWM power amplifier output, channel D.
36
HSBSD
I
HV
High-side boot strap input, output channel D. Capacitor couples to OUTD amplifier output.
37
HSBSC
I
HV
High-side boot strap input, output channel C. Capacitor couples to OUTC amplifier output.
38
OUTC
O
HV
PWM power amplifier output, channel C.
39
HGNDC
GND
HV
Output stage C high voltage supply ground. A separate ground pin connection is provided
for each of the output stages. All of the HGND[A:D] pins connect to system “HV” power
ground (also see Note 15).
40
HVDDC
P
HV
Output stage C high voltage supply power. A separate power pin connection is provided for
each of the output stages. All of the HVDD[A:D] pins and the VDDHV pin connect to the
system “HV” power source.
41
SUBOUT
O
3.3
“Subwoofer” channel PWM output, with 16mA drive strength. Connects to filter network for
supplying line-level analog output to subwoofer.
42
DNC
-
Do not connect to this pin.
Pin Description (Continued)
PIN
NAME
(Note 13) TYPE
VOLTAGE
LEVEL
(V)
DESCRIPTION
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