參數(shù)資料
型號: CYV15G0402DXB
廠商: Cypress Semiconductor Corp.
英文描述: Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
中文描述: 二,四的HOTLink SERDES的(四的HOTLink二并行轉(zhuǎn)換器)
文件頁數(shù): 27/29頁
文件大?。?/td> 634K
代理商: CYV15G0402DXB
CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 27 of 29
L02
L03
L04
L17
L18
L19
L20
M01
M02
M03
M04
M17
M18
M19
M20
N01
N02
N03
N04
N17
N18
N19
N20
P01
P02
P03
P04
P17
P18
P19
P20
R01
R02
R03
R04
R17
R18
R19
R20
T01
T02
T03
T04
RXCLKC+
TXCLKC
TXDC[6]
RXDB[8]
LFIB
RXCLKB–
TXDB[6]
RXDC[6]
RXDC[7]
RXDC[9]
RXDC[8]
TXDB[9]
TXDB[8]
TXDB[7]
TXCLKB
GND
GND
GND
GND
GND
GND
GND
GND
RXDC[3]
RXDC[2]
RXDC[1]
RXDC[0]
TXDB[5]
TXDB[4]
TXDB[3]
TXDB[2]
COMDETC
RXOPC
TXPERD
TXOPD
TXDB[1]
TXDB[0]
TXOPB
TXPERB
VCC
VCC
VCC
VCC
LVTTL I/O PD
LVTTL IN PD
LVTTL IN
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN PD
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL OUT
LVTTL 3-S OUT
LVTTL OUT
LVTTL IN PU
LVTTL IN
LVTTL IN
LVTTL IN PU
LVTTL OUT
POWER
POWER
POWER
POWER
T17
T18
T19
T20
U01
U02
U03
U04
U05
U06
U07
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
V01
V02
V03
V04
V05
V06
V07
V08
V09
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
VCC
VCC
VCC
VCC
TXDD[0]
TXDD[1]
TXDD[2]
TXDD[9]
VCC
RXDD[4]
RXDD[3]
GND
RXOPD
RFENC
REFCLK–
TXDA[1]
GND
TXDA[4]
TXDA[8]
VCC
RXDA[4]
RXOPA
COMDETA
RXDA[0]
TXDD[3]
TXDD[4]
TXDD[8]
RXDD[8]
VCC
RXDD[5]
RXDD[1]
GND
COMDETD
RFEND
REFCLK+
RFENB
GND
TXDA[3]
TXDA[7]
VCC
RXDA[9]
RXDA[5]
RXDA[2]
POWER
POWER
POWER
POWER
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL IN
POWER
LVTTL OUT
LVTTL OUT
GROUND
LVTTL 3-S OUT
LVTTL IN PD
PECL IN
LVTTL IN
GROUND
LVTTL IN
LVTTL IN
POWER
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
LVTTL IN
LVTTL IN
LVTTL OUT
POWER
LVTTL OUT
LVTTL OUT
GROUND
LVTTL OUT
LVTTL IN PD
PECL IN
LVTTL IN PD
GROUND
LVTTL IN
LVTTL IN
POWER
LVTTL OUT
LVTTL OUT
LVTTL OUT
V20
W01
W02
W03
W04
W05
W06
W07
W08
W09
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
RXDA[1]
TXDD[5]
TXDD[7]
LFID
RXCLKD–
VCC
RXDD[6]
RXDD[0]
GND
TXCLKO–
TXRST
TXOPA
RFENA
GND
TXDA[2]
TXDA[6]
VCC
LFIA
RXCLKA–
RXDA[6]
RXDA[3]
TXDD[6]
TXCLKD
RXDD[9]
RXCLKD+
VCC
RXDD[7]
RXDD[2]
GND
TXCLKO+
N/C
TXCLKA
TXPERA
GND
TXDA[0]
TXDA[5]
VCC
TXDA[9]
RXCLKA+
RXDA[8]
RXDA[7]
LVTTL OUT
LVTTL IN
LVTTL IN
LVTTL OUT
LVTTL OUT
POWER
LVTTL OUT
LVTTL OUT
GROUND
LVTTL OUT
LVTTL IN PU
LVTTL IN PU
LVTTL IN PD
GROUND
LVTTL IN
LVTTL IN
POWER
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL OUT
LVTTL IN
LVTTL IN
LVTTL OUT
LVTTL I/O PD
POWER
LVTTL OUT
LVTTL OUT
GROUND
LVTTL OUT
NO CONNECT
LVTTL IN PD
LVTTL OUT
GROUND
LVTTL IN
LVTTL IN
POWER
LVTTL IN
LVTTL I/O PD
LVTTL OUT
LVTTL OUT
Table 9. Package Coordinate Signal Allocation
(continued)
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
Ball
ID
Signal Name
Signal Type
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