參數(shù)資料
型號(hào)： CYV15G0402DXB
廠商： Cypress Semiconductor Corp.
英文描述： Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
中文描述： 二，四的HOTLink SERDES的（四的HOTLink二并行轉(zhuǎn)換器）
文件頁數(shù)： 20/29頁
文件大?。?/td> 634K
代理商： CYV15G0402DXB
CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 20 of 29
Maximum Ratings
(Above which the useful life may be impaired. User guidelines
only, not tested.
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
DC Voltage Applied to LVTTL Outputs
in High
Z State .......................................–0.5V to V
CC
+ 0.5V
Supply Voltage to Ground Potential...............–0.5V to +3.8V
Output Current into LVTTL Outputs (LOW)..................60 mA
DC Input Voltage....................................–0.5V to V
CC
+ 0.5V
CYP(V)15G0402DXB DC Electrical Characteristics
Over the Operating Range
Static Discharge Voltage..........................................> 2000 V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Power-up Requirements
The CYP(V)15G0402DXB requires one power supply. The
voltage on any input or I/O pin cannot exceed the power pin
during power-up.
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V ± 5%
3.3V ± 5%
Parameter
LVTTL-compatible Outputs
V
OHT
V
OLT
I
OST
I
OZL
LVTTL-compatible Inputs
V
IHT
V
ILT
I
IHT
Description
Test Conditions
Min.
Max.
Unit
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
High-Z Output Leakage Current
I
OH
= –4 mA, V
CC
= Min.
I
OL
= 4 mA, V
CC
= Min.
V
OUT
= 0V
[16]
2.4
0
–20
–20
V
CC
0.4
–100
20
V
V
mA
mA
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
2.0
–0.5
V
CC
+ 0.3
0.8
+1.5
+40
–1.5
–40
+200
–200
V
V
REFCLK Input, V
IN
= V
CC
Other Inputs, V
IN
= V
CC
REFCLK Input, V
IN
= 0.0V
Other Inputs, V
IN
= 0.0V
mA
μ
A
mA
μ
A
μ
A
μ
A
I
ILT
Input LOW Current
I
IHPDT
I
ILPUT
LVDIFF Inputs: REFCLK±
V
DIFF[17]
V
IHHP
V
ILLP
V
COMREF[18]
Three-level Inputs
V
IHH
V
IMM
V
ILL
I
IHH
I
IMM
I
ILL
Differential CML Serial Outputs: OUTA±, OUTB±, OUTC±, OUTD±
V
OHC
Output HIGH Voltage
Input HIGH Current with internal pull-down V
IN
= V
CC
Input LOW Current with internal pull-up
V
IN
= 0.0V
Input Differential Voltage
Highest Input HIGH Voltage
Lowest Input LOW voltage
Common Mode Range
400
1.2
0.0
1.0
V
CC
V
CC
V
CC
/2
V
CC
– 1.2V
mV
V
V
V
Three-level Input HIGH Voltage
Three-level Input MID Voltage
Three-level Input LOW Voltage
Input High Current
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
Vin = Vcc
0.87 * V
CC
0.47 * V
CC
0.0
V
CC
V
V
V
μ
A
μ
A
μ
A
0.53 * V
CC
0.13 * V
CC
200
Input MID Current
Vin = Vcc/2
–50
50
Input LOW Current
Vin = GND
–200
Typ.
Max.
V
CC
– 0.2
V
CC
– 0.2
Unit
V
V
100
differential load
150
differential load
V
CC
– 0.5
V
CC
– 0.5
Notes:
16. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
17. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when
the true (+) input is more positive than the complement (–) input. A logic-0 exists when the complement (-) input is more positive than true (+) input.
18. The common mode range defines the allowable range of REFCLK+ and REFCLK– when REFCLK+ = REFCLK–. This marks the zero-crossing between the
true and complement inputs as the signal switches between a logic-1 and a logic-0.
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