- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380227 > CYV15G0204TRB (Cypress Semiconductor Corp.) Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer PDF資料下載
參數(shù)資料
| 型號： | CYV15G0204TRB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| 中文描述： | 獨立時鐘的HOTLink二⑩雙串行解串器和雙時鐘重計 |
| 文件頁數(shù)： | 8/31頁 |
| 文件大?。?/td> | 389K |
| 代理商： | CYV15G0204TRB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
CYV15G0204TRB
Document #: 38-02101 Rev. *C
Page 8 of 31
Pin Definitions
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer
Name
Transmit Path Data and Status Signals
TXDA[7:0]
TXDB[7:0]
synchronous,
sampled by the
associated
TXCLKx
↑
or
REFCLKx
↑
[2]
TXERRA
TXERRB
synchronous to
REFCLKx
↑
[3]
,
asynchronous to
transmit channel
enable / disable,
asynchronous to loss
or return of
REFCLKx±
I/O Characteristics
Signal Description
LVTTL Input,
Transmit Data Inputs
. TXDx[9:0] data inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELx
latch via the device configuration interface.
LVTTL Output,
Transmit Path Error
. TXERRx is asserted HIGH to indicate detection of a transmit
Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is
detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted
until the transmit Phase-Align Buffer is re-centered with the PABRSTx latch via the
device configuration interface. When TXBISTx = 0, the BIST progress is presented
on the associated TXERRx output. The TXERRx signal pulses HIGH for one
transmit-character clock period to indicate a pass through the BIST sequence once
every 511 character times.
TXERRx is also asserted HIGH, when any of the following conditions is true:
The TXPLL for the associated channel is powered down. This occurs when OE2x
and OE1x for a given channel are both disabled by setting OE2x = 0 and OE1x = 0.
The absence of the REFCLKx± signal.
Transmit Path Clock Signals
REFCLKA±
REFCLKB±
Differential LVPECL
or single-ended
LVTTL input clock
Reference Clock
. REFCLKx± clock inputs are used as the timing references for the
transmit PLL. These input clocks may also be selected to clock the transmit parallel
interface. When driven by a single-ended LVCMOS or LVTTL clock source, connect
the clock source to either the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating). When driven by an LVPECL clock source,
the clock must be a differential clock, using both inputs.
Transmit Path Input Clock
. When configuration latch TXCKSELx = 0, the
associated TXCLKx input is selected as the character-rate input clock for the
TXDx[9:0] input. In this mode, the TXCLKx input must be frequency-coherent to its
associated TXCLKOx output clock, but may be offset in phase by any amount. Once
initialized, TXCLKx is allowed to drift in phase as much as ±180 degrees. If the input
phase of TXCLKx drifts beyond the handling capacity of the Phase Align Buffer,
TXERRx is asserted to indicate the loss of data, and remains asserted until the
Phase Align Buffer is initialized. The phase of the TXCLKx input clock relative to its
associated REFCLKx± is initialized when the configuration latch PABRSTx is written
as 0. When the associated TXERRx is deasserted, the Phase Align Buffer is
initialized and input characters are correctly captured.
Transmit Clock Output
. TXCLKOx output clock is synthesized by each channel’s
transmit PLL and operates synchronous to the internal transmit character clock.
TXCLKOx operates at either the same frequency as REFCLKx± (TXRATEx = 0), or
at twice the frequency of REFCLKx± (TXRATEx = 1). The transmit clock outputs
have no fixed phase relationship to REFCLKx±.
TXCLKA
TXCLKB
LVTTL Clock Input,
internal pull-down
TXCLKOA
TXCLKOB
LVTTL Output
Notes
2. When REFCLKx± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx±.
3. When REFCLKx± is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx±.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0204TRB-BGC | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGXC | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0401DXB | Quad HOTLink II Transceiver |
| CYV15G0401DXB-BGC | Quad HOTLink II Transceiver |
| CYV15G0401DXB-BGI | Quad HOTLink II Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0204TRB-BGC | 功能描述:視頻 IC 2x Indep Reclocker Serializer COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204TRB-BGXC | 功能描述:視頻 IC 2x Indep Reclocker Serializer COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0401DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ Transceiver |
| CYV15G0401DXB-BGC | 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0401DXB-BGI | 功能描述:電信線路管理 IC Quad Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。