
CYV15G0204TRB
Document #: 38-02101 Rev. *C
Page 11 of 31
DATA[6:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus
. The DATA[6:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[6:0] bus into the latch
specified by address location on the ADDR[3:0] bus.
[5]
Table 4 on page 16
lists the
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET.
Table 5 on page 18
shows how the latches are mapped in
the device.
Internal Device Configuration Latches
RXRATE[C..D]
Internal Latch
[6]
SDASEL[2..1][C..D]
[1:0]
TXCKSEL[A..B]
Internal Latch
[6]
TXRATE[A..B]
Internal Latch
[6]
TRGRATE[C..D]
Internal Latch
[6]
RXPLLPD[C..D]
Internal Latch
[6]
RXBIST[C..D][1:0]
Internal Latch
[6]
TXBIST[A..B]
Internal Latch
[6]
TOE2[A..B]
Internal Latch
[6]
TOE1[A..B]
Internal Latch
[6]
ROE2[C..D]
Internal Latch
[6]
ROE1[C..D]
Internal Latch
[6]
PABRSTB[A..B]
Internal Latch
[6]
Factory Test Modes
SCANEN2
LVTTL input,
internal pull-down
TMEN3
LVTTL input,
internal pull-down
Analog I/O
TOUTA1±
TOUTB1±
Output
Receive Clock Rate Select
.
Signal Detect Amplitude Select
.
Internal Latch
[6]
Transmit Clock Select
.
Transmit PLL Clock Rate Select
.
Reclocker Output PLL Clock Rate Select
.
Receive Channel Power Control
.
Receive Bist Disabled
.
Transmit Bist Disabled
.
Transmitter Differential Serial Output Driver 2 Enable
.
Transmitter Differential Serial Output Driver 1 Enable
.
Reclocker Differential Serial Output Driver 2 Enable
.
Reclocker Differential Serial Output Driver 1 Enable
.
Transmit Clock Phase Alignment Buffer Reset
.
Factory Test 2.
SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
Factory Test 3
. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
CML Differential
Transmitter Primary Differential Serial Data Output
. The transmitter TOUTx1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be
AC-coupled for PECL-compatible connections.
Transmitter Secondary Differential Serial Data Output
. The transmitter TOUTx2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
Reclocker Primary Differential Serial Data Output
. The reclocker ROUTx1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be
AC-coupled for PECL-compatible connections.
Reclocker Secondary Differential Serial Data Output
. The reclocker ROUTx2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-
mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
Primary Differential Serial Data Input
. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELx = HIGH.
TOUTA2±
TOUTB2±
CML Differential
Output
ROUTC1±
ROUTD1±
CML Differential
Output
ROUTC2±
ROUTD2±
CML Differential
Output
INC1±
IND1±
Differential Input
Note
6. See
Device Configuration and Control Interface
for detailed information on the internal latches.
Pin Definitions
(continued)
CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer
Name
I/O Characteristics
Signal Description
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